Variable-speed line adapter for synchronous transmissions

Claim 2

In a line adapter for data transmission systems in which any of a plurality of different transmission speed terminals may transmit data to said line adapter and in which each data transmission is preceded by one or more signal groups representing a predetermined character a plurality of clock controlling circuits, one for each transmission speed to be received by said line adapter, selecting means for said clock controlling circuits, means initially activated to cause selection of one of said clock-controlling circuits cyclic timing circuits for said line adapter set into action by a first character signal from a terminal, means controlled by said timing circuits to detect a signal level transition in the received data, means to count said signal level transitions found by said detecting means, an interval timer responsive to said timing circuits to indicate the end of the time interval needed for receipt of a predetermined character at the initially selected transmission speed and control means to change said selecting means for said clock control circuits to select a different clock control circuit when the number of signal level transitions which have been counted when the end of the time interval is indicated is different from the actual number of transitions in said predetermined character said initially activated means also being operative to restore said level transition counter to an initial condition.

Claim 3

A line adapter as in claim 1 in which said signal level transition detecting means includes a pair of bit storage devices, means controlled by said timing circuits to periodically set a first of said storage devices in accordance with the level of the received data signal, transfer means also controlled by said timing circuits to transfer the setting of said first storage device to the other of said storage devices, and in which said means to detect a signal level transition comprises circuits to detect a difference in the set states of said storage devices.

Claim 4

A line adapter for data transmission systems in which any of plurality of different transmission speed terminals may transmit to said line adapter and in which each data transmission is preceded by one or more signal groups representing a predetermined character, said line adapter comprising a cyclic timing means including a plurality of oscillator circuits, one for each transmission speed to be received, an oscillator selection means to select one of said oscillator circuits for control over said cyclic timing means, initializing means to set said selecting means to one condition, a timer activating circuit to initiate operation of said timing means at the start of reception of signals from a terminal, bit sampling means controlled by said cyclic timing means, a shift register responsive to said bit sampling means and said timing means to store indications of at least the last two data samples, signal transition means to compare the states of the stored indications to detect the occurrence of a transition in said signal, a signal transition counter to count the transitions detected by said signal transition means, a character interval detector driven by said bit sampling means to indicate when enough time has passed for a predetermined character to have been received and means controlled by said cyclic timing means, said transition counter and said character interval detector to activate said oscillator selection means to cause selection of a different oscillator circuit if the number of signal transitions counted during the first character interval does not correspond to the number of transitions in said predetermined character.

Claim 5

A line adapter for data transmission systems in which any of plurality of different transmission speed terminals may transmit to said line adapter and in which each data transmission is preceded by one or more signal groups representing a predetermined character, said line adapter comprising a cyclic timing means including a plurality of oscillator circuits, one for each transmission speed to be received, an oscillator selection means to select one of said oscillator circuits for control over said cyclic timing means, initializing means to set said selecting means to one condition, a timer activating circuit to initiate operation of said timing means at the start of reception of signals from a terminal, bit sampling means controlled by said cyclic timing means, a shift register responsive to said bit sampling means and said timing means to store indications of at least the last two data samples, signal transition means to compare the states of the stored indications to detect the occurrence of a transition in said signal, a signal transition counter to count the transitions detected by said signal transition means, a character interval detector driven by said bit sampling means to indicate when enough time has passed for a predetermined character to have been received and means controlled by said cyclic timing means, said transition counter and said character interval detector to activate said oscillator selection means to cause selection of a different oscillator circuit if the number of signal transitions counted during the first character interval does not correspond to the number of transitions in said predetermined character.

Claim 6

A line adapter for receiving data transmissions of at least two different speeds, said adapter comprising a timing means for determining bit sampling times, said timing means including at least a pair of oscillator circuits, oNe for each transmission speed and oscillator selection means initially set to select one oscillator circuit to control the operation rate of said timing means, a received data circuit to initiate operation of said timing means at the start of reception of data transmission, a two stage shift register controlled by said timing means to receive data bit samples from said received data circuit, a transition counter driven whenever the successive data bit samples stored in said shift register are different, a sample counter driven by said timing means to count the number of data bit samples, a character end decoder sampling said sample counter and signaling when sufficient time has elapsed to allow receipt of a character at a first transmission rate and an oscillator selection control circuit responsive to said character end decoder, said transition counter and said timing means to set said oscillator selection means to select another oscillator circuit when the initially selected oscillator circuit is not operating at the transmission speed of the first received character.

Claim 7

A line adapter for receiving data transmissions of at least two different speeds, said adapter comprising a timing means for determining bit sampling times, said timing means including at least a pair of oscillator circuits, oNe for each transmission speed and oscillator selection means initially set to select one oscillator circuit to control the operation rate of said timing means, a received data circuit to initiate operation of said timing means at the start of reception of data transmission, a two stage shift register controlled by said timing means to receive data bit samples from said received data circuit, a transition counter driven whenever the successive data bit samples stored in said shift register are different, a sample counter driven by said timing means to count the number of data bit samples, a character end decoder sampling said sample counter and signaling when sufficient time has elapsed to allow receipt of a character at a first transmission rate and an oscillator selection control circuit responsive to said character end decoder, said transition counter and said timing means to set said oscillator selection means to select another oscillator circuit when the initially selected oscillator circuit is not operating at the transmission speed of the first received character.

Claim 8

The line adapter as set out in claim 4 including an adapter initializing circuit activated in advance of reception of a data transmission to reset said transition counter and said shift register, to initially set said oscillator selection means to select a predetermined one of said oscillator circuits and to set an initialize latch which frees the oscillator selection control circuit to change the initial setting of said oscillator selection means and a circuit controlled by said character end decoder and said timing means to reset said initialize latch to thereafter retain the selected one of said oscillator circuits in control of said timing means.