Adaptive delay line equalizer for waveforms with correlation between subsequent data bits

Claim 2

An adaptive delay line equalizer comprising: supply means for supplying a plurality of sequential data bits; amplification means connected to each of said supply means modifying the output of said supply means; summing means connected to the output of said amplifying means producing a signal equal to the sum of said outputs; detector means connected to the output of said summing means and producing at least two different outputs descriptiVe of said sum; and multiplication means multiplying the outputs from said detector means with one another and with previous outputs of said detector means and said products from at least two multipliers controlling the amplification of said amplification means, the output of said amplifications representing the equalized waveform.

Claim 3

An adaptive delay line equalizer as in claim 1 wherein the detector means produces three outputs: a first signal representing the sign of the signal output of said summing means, a second signal representing the sign of the error of said first signal, and a third signal indicating if the signal output from said summing amplifier represents a zero voltage.

Claim 4

An adaptive delay line equalizer comprising: supply means for supplying 2N+1 sequential data bits where N is positive integer; amplification means connected to each of said supply means modifying the output of said supply means; summing means connected to the output of said amplifying means producing a signal equal to the sum of all of said outputs; detector means connected to the output of said summing means and producing three outputs: a first signal representing the sign of the signal output of said summing means (sgn ak), a second signal representing the sign of the error of said first signal (sgn ek), and a third signal indicating if the signal output from said summing amplifier represents a zero voltage (0k); delay means connected to each of the outputs of said detector means; 2N+1 multiplication means connected to the outputs of said delay means where the jth multiplier produces the products (sgn ak) (sgn ek), 1/2 (sgn ak) (sgn ek) and 1/2 (sgn ak) (sgn ek 2), where j is an integer between -N and N; and control means connected to the output of a plurality of multiplier means and to said amplification means, said control means, in accordance with its input, controlling the amplification of said amplifier means, the output of said amplifier representing the equalized waveform.

Claim 5

An adaptive delay line equalizer comprising: supply means for supplying 2N+1 sequential data bits where N is positive integer; amplification means connected to each of said supply means modifying the output of said supply means; summing means connected to the output of said amplifying means producing a signal equal to the sum of all of said outputs; detector means connected to the output of said summing means and producing three outputs: a first signal representing the sign of the signal output of said summing means (sgn ak), a second signal representing the sign of the error of said first signal (sgn ek), and a third signal indicating if the signal output from said summing amplifier represents a zero voltage (0k); delay means connected to each of the outputs of said detector means; 2N+1 multiplication means connected to the outputs of said delay means where the jth multiplier produces the products (sgn ak) (sgn ek), 1/2 (sgn ak) (sgn ek) and 1/2 (sgn ak) (sgn ek 2), where j is an integer between -N and N; and control means connected to the output of a plurality of multiplier means and to said amplification means, said control means, in accordance with its input, controlling the amplification of said amplifier means, the output of said amplifier representing the equalized waveform.

Claim 6

An adaptive delay line equalizer comprising: a delay line having 2N+1 taps equally spaced therealong, where N is a positive integer; attenuators connected to each of the taps of said delay line; a summing amplifier connected to the output of said attenuators producing a signal equal to the sum of all said outputs; a threshold detector connected to the output of said summing amplifier and having a first output producing a first signal representing the sign of the signal output of said summing amplifier (ak), a second output producing a second signal representing the sign of the error of said first signal (ek), and a third output producing a third signal indicating if the signal from said summing amplifier represents a zero voltage (0k); a first shift register connected to said threshold detector having at its outputs ek and ek 2; a second shift register connected to said threshold detector producing at its outputs sgn ak n to sgn ak n; and third shift register connected to said threshold detector producing at its outputs 0k n to 0k n; 2N+1 multipliers, a first of said multipliers being connected to each output of said first shift register and to said first and third outputs of said threshold detector, each of the remaining of said multipliers being connected to each of output of said first shift register and to respective stages of said second and said third shift registers, such that the jth multiplier produces the products (sgn ak j) (sgn ek), 1/2 (sgn ak j) (sgn ek), and 1/2 (sgn ak j) (sgn ek 2); 2N+1 storage counters, a first of said storage counters being connected to said first of said multipliers, a second of said storage counters being connected to a second of said multipliers, each of the remaining of said storage counters being connected to a respective multiplier and to a twice proceeding multiplier, such that the jth storage counter sums the following outputs: (sgn ek) (sgn ak j) + 1/2 (sgn ek) (sgn ak 2 j) + 1/2 (sgn ek 2) (sgn ak j), said storage counter overflowing or underflowing when a certain count has been reached in either direction, thereby averaging its inputs; and control means connected to the output of said storage counter and to said attenuators, increasing or decreasing the attenuation of said attenuators depending upon whether said storage counter overflows or underflows, the output of said amplifier representing the equalized waveform.

Claim 7

An adaptive delay line equalizer comprising: a delay line having 2N+1 taps equally spaced therealong, where N is a positive integer; attenuators connected to each of the taps of said delay line; a summing amplifier connected to the output of said attenuators producing a signal equal to the sum of all said outputs; a threshold detector connected to the output of said summing amplifier and having a first output producing a first signal representing the sign of the signal output of said summing amplifier (ak), a second output producing a second signal representing the sign of the error of said first signal (ek), and a third output producing a third signal indicating if the signal from said summing amplifier represents a zero voltage (0k); a first shift register connected to said threshold detector having at its outputs ek and ek 2; a second shift register connected to said threshold detector producing at its outputs sgn ak n to sgn ak n; and third shift register connected to said threshold detector producing at its outputs 0k n to 0k n; 2N+1 multipliers, a first of said multipliers being connected to each output of said first shift register and to said first and third outputs of said threshold detector, each of the remaining of said multipliers being connected to each of output of said first shift register and to respective stages of said second and said third shift registers, such that the jth multiplier produces the products (sgn ak j) (sgn ek), 1/2 (sgn ak j) (sgn ek), and 1/2 (sgn ak j) (sgn ek 2); 2N+1 storage counters, a first of said storage counters being connected to said first of said multipliers, a second of said storage counters being connected to a second of said multipliers, each of the remaining of said storage counters being connected to a respective multiplier and to a twice proceeding multiplier, such that the jth storage counter sums the following outputs: (sgn ek) (sgn ak j) + 1/2 (sgn ek) (sgn ak 2 j) + 1/2 (sgn ek 2) (sgn ak j), said storage counter overflowing or underflowing when a certain count has been reached in either direction, thereby averaging its inputs; and control means connected to the output of said storage counter and to said attenuators, increasing or decreasing the attenuation of said attenuators depending upon whether said storage counter overflows or underflows, the output of said amplifier representing the equalized waveform.

Claim 8

An adaptive delay line equalizer as in claim 4 where N 12, and where said storage counters have a capacity of 256 counts in both directions.