Program controlled data processing system

Claim 2

In combination: a memory arrangement; and a central control comprising: means for reading information from said memory arrangement, a multibit data register, and a mask circuit connected to the input terminals of said data register, said mask circuit comprising a plurality of gating circuits, one of said gating circuits being uniquely associated with each bit position of said data register, each of said gating circuits having input terminals connected to a data input source and to a masking input source corresponding to the associated bit position of said data register, said gating circuits being arranged to insert data from said data sources only into the bit positions of said data register for which the corresponding masking input sources are enabled.

Claim 3

The combination in accordance with claim 3 wherein said central control further comprises in combination: an instruction store; a data store; a central control responsive to program order words read from said instruction store and to data read from said data store; a data buffer register system comprising a data buffer register, a plurality of auxiliary buffer register circuits, a data buffer register output bus connecting the output terminals of said data buffer register to said auxiliary buffer register circuits, and a data buffer register input bus connecting said auxiliary buffer register circuits to the input terminals of said data buffer register; transmission means for transmitting data from said data store to said data buffer register; and said central control comprising a common transmission bus, a logic register, and an insertion mask circuit for selectively transmitting information from said common transmission bus to particular bit positions of said data buffer register in accordance with the contents of said logic register.

Claim 4

The combination according to claim 2 wherein said insertion mask circuit includes means for transmitting to said data buffer register the information appearing on said common transmission bus at each bit position corresponding to a bit position of said logic register wherein a logical 1 occurs.

Claim 5

A telephone switching system comprising: a plurality of communication paths; a switching network for selectively interconnecting said communication paths; a scanner system for scanning said communication paths and portions of said switching network; a program store; a call store; a central control; means in said central control for reading information from said program store; means in said central control for reading information from said call store; an unmasked bus; a masked bus; a mask circuit interposed between said unmasked bus and said masked bus; a logic register connected to masking input terminals of said mask circuit; a buffer register system comprising a data buffer register for receiving information read from said call store and for storing information to be transmitted to said call store; a buffer register output bus; a plurality of auxiliary buffer register circuits connected to said buffer register output bus; a buffer register input bus connecting said auxiliary buffer register circuits to said buffer register; means connecting said buffer register output bus to input terminals of said mask circuit; and means responsive to said information read from said program store for generating control signals for said mask circuit.

Claim 6

A telephone switching system comprising: a plurality of communication paths; a switching network for selectively interconnecting said communication paths; a scanner system for scanning said communication paths and portions of said switching network; a program store; a call store; a central control; means in said central control for reading information from said program store; means in said central control for reading information from said call store; an unmasked bus; a masked bus; a mask circuit interposed between said unmasked bus and said masked bus; a logic register connected to masking input terminals of said mask circuit; a buffer register system comprising a data buffer register for receiving information read from said call store and for storing information to be transmitted to said call store; a buffer register output bus; a plurality of auxiliary buffer register circuits connected to said buffer register output bus; a buffer register input bus connecting said auxiliary buffer register circuits to said buffer register; means connecting said buffer register output bus to input terminals of said mask circuit; and means responsive to said information read from said program store for generating control signals for said mask circuit.

Claim 7

In combination: a memory containing sequences of program order words and data; and a central control which generates control signals in response to execution of said order words and comprising: means for reading information from said memory, a plurality of flip-flops registers, an unmasked bus connected to the output terminals of said flip-flop registers, a masked bus connected to the input terminals of said flip-flop registers, a mask circuit interposed between said unmasked bus and said masked bus having data input terminals, masking input terminals and data output terminals, said mask circuit being responsive to said control signals for defining a particular logical operation to be performed in said mask circuit, said unmasked bus connected to said data input terminals of said mask circuit, the output terminals of one of said flip-flop registers connected to said masking input terminals, said data output terminals of said mask circuit connected to said masked bus, an order word register for storing certain of said information read from said memory, and a plurality of stages of said order word register being selectively connectable to the input terminals of said one of said flip-flop rEgisters,

Claim 8

In combination: a memory containing sequences of program order words and data; and a central control which generates control signals in response to execution of said order words and comprising: means for reading information from said memory, a plurality of flip-flops registers, an unmasked bus connected to the output terminals of said flip-flop registers, a masked bus connected to the input terminals of said flip-flop registers, a mask circuit interposed between said unmasked bus and said masked bus having data input terminals, masking input terminals and data output terminals, said mask circuit being responsive to said control signals for defining a particular logical operation to be performed in said mask circuit, said unmasked bus connected to said data input terminals of said mask circuit, the output terminals of one of said flip-flop registers connected to said masking input terminals, said data output terminals of said mask circuit connected to said masked bus, an order word register for storing certain of said information read from said memory, and a plurality of stages of said order word register being selectively connectable to the input terminals of said one of said flip-flop rEgisters,

Claim 9

A data processor of a program controlled telephone switching system comprising: a program store containing sequences of program order words and data words, said data words each comprising a first and a second portion; said program store comprising a plurality of word locations each of said word locations containing n bits of information; a data store containing a plurality of data words each of said data words comprising (n/2 + m) bits; a central control comprising means for generating commands for reading information from said program store and said data store; said means including means for generating a binary word representative of a data word to be read from said program store; translating means responsive to said binary word for generating commands for reading said data word from said program store; and instruction execution means in said central control responsive to a portion of said binary word for selectively processing therein a first or a second portion of said data word read from said program store.

Claim 10

A data processor of a program controlled telephone switching system comprising: a program store containing sequences of program order words and data words, said data words each comprising a first and a second portion; said program store comprising a plurality of word locations each of said word locations containing n bits of information; a data store containing a plurality of data words each of said data words comprising (n/2 + m) bits; a central control comprising means for generating commands for reading information from said program store and said data store; said means including means for generating a binary word representative of a data word to be read from said program store; translating means responsive to said binary word for generating commands for reading said data word from said program store; and instruction execution means in said central control responsive to a portion of said binary word for selectively processing therein a first or a second portion of said data word read from said program store.

Claim 11

A data processor of a program controlled telephone switching system comprising: a program store having a plurality of n bit memory locations, certain of said locations containing program order words, other of said locations containing data, said data comprising a first data base word, a second data base word, a plurality of data word prefix bits assignable to said first data base word in a first sequential order and assignable to said second data base word in the inverse order of said first sequential order; means in said central control for generating commands for reading data from said program store; and means for selecting for processing said first data base word and said prefix bits and for selecting for processing said second data base word and said data prefix bits.

Claim 12

A data processor of a program controlled telephone switching system comprising: a program store having a plurality of n bit memory locations, certain of said locations containing program order words, other of said locations containing data, said data comprising a first data base word, a second data base word, a plurality of data word prefix bits assignable to said first data base word in a first sequential order and assignable to said second data base word in the inverse order of said first sequential order; means in said central control for generating commands for reading data from said program store; and means for selecting for processing said first data base word and said prefix bits and for selecting for processing said second data base word and said data prefix bits.

Claim 13

A data processor in accordance with claim 7 wherein said means for selecting comprises means for selecting any number of said prefix bits.

Claim 14

In combination: a program store containing sequences of program order words, certain of said order words, including memory-accumulator combining orders, representing single cycle orders and other of said order words representing multicycle orders; a data store; and a central control comprising; means responsive to certain of said order words for generating code-addresses for reading information from said program store and from said data store, a plurality of registers including an accumulator register, a first accumulator input register, a second accumulator input register, means responsive to gating signals for transmitting the contents of said accumulator register to certain ones of said plurality of registers, accumulator input means for logically combining the contents of said first and said second input registers in accordance with input means control signals, decoder means responsive to said memory-accumulator combining orders for generating code-addresses for reading data words from said data store at a memory location specified in said memory-accumulator combining order, means for resetting said accumulator second input register, means for transmitting the contents of said accumulator register to said accumulator second input register, and means for generating said control signals for said input means and for generating said gating signals, and said last named means including an accumulator sequencer responsive to output signals of said decoder means for extending the data processing time for memory-accumulator combining orders beyond a period of time required to execute other single cycle orders and thereby extends the degree of operational overlap between a memory-accumulator combining order and a succeeding order.

Claim 15

In combination: a program store containing sequences of program order words, certain of said order words, including memory-accumulator combining orders, representing single cycle orders and other of said order words representing multicycle orders; a data store; and a central control comprising; means responsive to certain of said order words for generating code-addresses for reading information from said program store and from said data store, a plurality of registers including an accumulator register, a first accumulator input register, a second accumulator input register, means responsive to gating signals for transmitting the contents of said accumulator register to certain ones of said plurality of registers, accumulator input means for logically combining the contents of said first and said second input registers in accordance with input means control signals, decoder means responsive to said memory-accumulator combining orders for generating code-addresses for reading data words from said data store at a memory location specified in said memory-accumulator combining order, means for resetting said accumulator second input register, means for transmitting the contents of said accumulator register to said accumulator second input register, and means for generating said control signals for said input means and for generating said gating signals, and said last named means including an accumulator sequencer responsive to output signals of said decoder means for extending the data processing time for memory-accumulator combining orders beyond a period of time required to execute other single cycle orders and thereby extends the degree of operational overlap between a memory-accumulator combining order and a succeeding order.

Claim 16

The combination in accordance with claim 9 wherein said accumulator input means comprises means for providing at the output terminals thereof a data word which is: a. the arithmetic sum of the contents of said first and said second accumulator input registers; b. the logical AND of the contents of said first and said second accumulator input registers; c. the logical OR of the contents of said first and said second accumulator input registers; and d. the EXCLUSIVE-OR of the contents of said first and said second accumulator input registers, said accumulator sequencer providing control signals to said accumulator input means to cause said input means to provide a selected one of a. through d. above.

Claim 17

The combination in accordance with claim 9 wherein said accumulator sequencer in response to output signals from said decoder means generates selected gating signals for gating output signals of said accumulator input means to a specified one of said certain registers.

Claim 18

In combination: a program store containing sequences of program order words and system data, each of said order words comprising an instruction field and an N bit data field; a data store containing a plurality of N bit data words; and a central control comprising; means for obtaining information from said stores and for writing data into said data store, means for executing said sequences of program order words, a plurality of N bit flip-flop registers, data processing means for processing N bit data words, and means responsive to the execution of said sequences of program order words for generating control signals for controlling said data processing means.

Claim 19

In combination: a program store containing sequences of program order words and system data, each of said order words comprising an instruction field and an N bit data field; a data store containing a plurality of N bit data words; and a central control comprising; means for obtaining information from said stores and for writing data into said data store, means for executing said sequences of program order words, a plurality of N bit flip-flop registers, data processing means for processing N bit data words, and means responsive to the execution of said sequences of program order words for generating control signals for controlling said data processing means.

Claim 20

In combination: a memory system containing sequences of program order words and system data; a central control comprising, means for generating commands for obtaining information from said memory system; means for executing said sequences of program order words; a plurality of flip-flop registers; a data buffer register; first transmission means interconnecting said memory system and said data buffer register for transmitting information obtained from said memory system to said data buffer register; second transmission means for transmitting the contents of said data buffer register to a selected one of said flip-flop registers; said second transmission means comprising an unmasked bus, a mask and complement circuit and a masked bus; and means for controlling said mask and complement circuit.

Claim 21

In combination: a memory system containing sequences of program order words and system data; a central control comprising, means for generating commands for obtaining information from said memory system; means for executing said sequences of program order words; a plurality of flip-flop registers; a data buffer register; first transmission means interconnecting said memory system and said data buffer register for transmitting information obtained from said memory system to said data buffer register; second transmission means for transmitting the contents of said data buffer register to a selected one of said flip-flop registers; said second transmission means comprising an unmasked bus, a mask and complement circuit and a masked bus; and means for controlling said mask and complement circuit.

Claim 22

The combination in accordance with claim 13 wherein said memory system comprises a program store containing said sequences of program order words and certain of said data, and a data store containing other of said data, and wherein said transmission means interconnecting said memory system and said data buffer register comprises: a. a data store response bus, and data store response selection gates interconnecting said data store and said data buffer register; and b. a program store response transmission bus, program store response selection gates, a buffer order word register, an index adder system, said mask and complement circuit, said masked bus, and gating means interposed between said masked bus and said data buffer register.

Claim 23

In combination: a program store containing sequences of program order words and system data, said sequences of program order words including indexing order words; a data store containing system data; a central control comprising means for generating commands for obtaining information from said stores and to write information into said data store; means for executing said sequences of program order words; a data buffer register for storing information to be written into said data store and for receiving information read from said data store; transmission means interconnecting said data store and said data buffer register; a plurality of index registers including said data buffer register; an index adder system comprising a plurality of input registers, an index adder and an index adder output register; transmission and gating means interposed between said plurality of index registers and said input registers of said index adder system; and means responsive to said indexing program order words for generating control signals for gating the contents of a selected index register and a portion of said indexing order word to said index adder input registers and for controlling said index adder system.

Claim 24

In combination: a program store containing sequences of program order words and system data, said sequences of program order words including indexing order words; a data store containing system data; a central control comprising means for generating commands for obtaining information from said stores and to write information into said data store; means for executing said sequences of program order words; a data buffer register for storing information to be written into said data store and for receiving information read from said data store; transmission means interconnecting said data store and said data buffer register; a plurality of index registers including said data buffer register; an index adder system comprising a plurality of input registers, an index adder and an index adder output register; transmission and gating means interposed between said plurality of index registers and said input registers of said index adder system; and means responsive to said indexing program order words for generating control signals for gating the contents of a selected index register and a portion of said indexing order word to said index adder input registers and for controlling said index adder system.

Claim 25

A data processing system comprising a memory arrangement and a central processor, said central processor comprising: an arithmetic logic unit; a first data transfer bus connected to input terminals of said arithmetic logic unit; a second data transfer bus connected to output terminals of said arithmetic logic unit; a plurality of flip-flop registers having input terminals connected to said second data transfer bus and output terminals connected to said first data transfer bus; a buffer register system comprising a data buffer register for buffering data communicated between said memory and said central processor; a mask register; and an insertion mask circuit connected to input terminals of said data buffer register for selectively inserting data appearing on said second data transfer bus into bit positions of said data buffer register specified by the contents of said mask register.

Claim 26

A data processing system comprising a memory arrangement and a central processor, said central processor comprising: an arithmetic logic unit; a first data transfer bus connected to input terminals of said arithmetic logic unit; a second data transfer bus connected to output terminals of said arithmetic logic unit; a plurality of flip-flop registers having input terminals connected to said second data transfer bus and output terminals connected to said first data transfer bus; a buffer register system comprising a data buffer register for buffering data communicated between said memory and said central processor; a mask register; and an insertion mask circuit connected to input terminals of said data buffer register for selectively inserting data appearing on said second data transfer bus into bit positions of said data buffer register specified by the contents of said mask register.

Claim 27

A data processing system in accordance with claim 16 wherein said arithmetic logic unit comprises a plurality of logic gates for selectively combining the contents of said mask register and data appearing on said first data transfer bus.

Claim 28

In combination: a memory containing sequences of program order words, certain of said order words comprising an instruction portion and an address portion; and a central processor comprising: memory addressing means for reading information from said memory and writing information into said memory, a plurality of index registers, an index adder arrangement, and execution means responsive to the instruction portion of said certain order words to control the execution thereof and to selectively generate control signals for adding the contents of a specified one of said index registers to the address portion of said certain order words and to transmit the resulting data word to said specified index register and said memory addressing means.

Claim 29

In combination: a memory containing sequences of program order words, certain of said order words comprising an instruction portion and an address portion; and a central processor comprising: memory addressing means for reading information from said memory and writing information into said memory, a plurality of index registers, an index adder arrangement, and execution means responsive to the instruction portion of said certain order words to control the execution thereof and to selectively generate control signals for adding the contents of a specified one of said index registers to the address portion of said certain order words and to transmit the resulting data word to said specified index register and said memory addressing means.

Claim 30

In combination: a memory arrangement containing sequences of program order words, certain of said order words including an instruction portion and an address portion; and a central processor comprising: memory addressing means for obtaining information from said memory and for writing information into said memory, a plurality of index registers, and execution means responsive to the instruction portion of said certain order words to control the execution thereof and to transmit the address portion of said certain order words to said memory addressing means and to a specified one of said index registers.

Claim 31

In combination: a memory arrangement containing sequences of program order words, certain of said order words including an instruction portion and an address portion; and a central processor comprising: memory addressing means for obtaining information from said memory and for writing information into said memory, a plurality of index registers, and execution means responsive to the instruction portion of said certain order words to control the execution thereof and to transmit the address portion of said certain order words to said memory addressing means and to a specified one of said index registers.