Abstract Apparatus for controlling the rate at which information is transferred from the output of a multistage storage register in accordance with the rate at which information is supplied to the input of the register. A pulse generator supplies a first pulse train of equidistantly spaced pulses of like amplitude and duration to a ''''divide by N'''' counter where N is a variable integer. The output of the counter yields a second pulse train of variable recurrence frequency which is used to control the information transfer rate from the output of the register. The rate at which information is supplied to the input of the register varies, thus varying the amount of information stored in the register. A logic circuit is interposed between the buffer and the counter to vary the value of N in accordance with the changes in the amount of information stored in the register in such manner that the average rate at which information is transferred from the output of the register is always equal to the average rate at which information is supplied to the input of the register.
Apparatus for controlling the rate of transfer of information out of the last stage of a multistage register which receives incoming information at a variable rate, said register having A different stages where A is an integer, each stage having an associated device for indicating whether the corresponding stage is either filled with information or is empty, said apparatus comprising: a pulse generator for producing a first pulse train at a fixed recurrence frequency; a ''''divide by N'''' counter, where N is a variable integer, said counter receiving said first pulse train at its input and yielding at its output a second pulse train of variable recurrence frequency; means to supply said second train to said register, each second train pulse initiating the transfer of information out of said last stage; means coupled to each of said devices in the register and responsive to the number of filled stages therein to produce a digital control signal which varies with changes in the number of filled stages, said digital signal attaining any one of A different values; and means to supply said digital signal to said counter to determine the value of N in such manner that the average rate of transfer of information out of the register is always equal to the average rate at which information is supplied to the input of the register.
Claim 2
Dependent Claim
225 words
Apparatus for controlling the rate of transfer of information out of the last stage of a multistage register which receives incoming information at a variable rate, said register having A different stages where A is an integer, each stage having an associated device for indicating whether the corresponding stage is either filled with information or is empty, said apparatus comprising: a pulse generator for producing a first pulse train at a fixed recurrence frequency; a ''''divide by N'''' counter, where N is a variable integer, said counter receiving said first pulse train at its input and yielding at its output a second pulse train of variable recurrence frequency; means to supply said second train to said register, each second train pulse initiating the transfer of information out of said last stage; means coupled to each of said devices in the register and responsive to the number of filled stages therein to produce a digital control signal which varies with changes in the number of filled stages, said digital signal attaining any one of A different values; and means to supply said digital signal to said counter to determine the value of N in such manner that the average rate of transfer of information out of the register is always equal to the average rate at which information is supplied to the input of the register.
Claim 3
Dependent Claim
44 words
Apparatus as set forth in claim 1 wherein each device is a flip-flop which is in a selected one of its two electric states when its corresponding stage is filled and is in the other of said states when the corresponding stage is empty.
Claim 4
Dependent Claim
15 words
Apparatus as set forth in claim 1 wherein said responsive means is a logic circuit.