Patent US2143627A successfully refreshed from Google Patents.
US3562494A
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Code detecting and control circuit for sorting articles
Assignee: FMC Corp
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Filing: 1967-11-24
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Granted: 1971-02-09
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Expires: 1987-11-24
Abstract
Abstract A code detecting and control circuit in which a reader senses label identification indicia to first determine whether the label viewed is the intended label and then samples destination code indicia during clock pulse time initiated by clock pulse marks on the label. Prearranged sets of light sensing devices in the reader not only read the indicia on the label but check the width of clock pulse marks and the space between successive clock pulse marks to verify the authenticity of the marks controlling time sampling of the destination code indicia.
Inventors
- 👤 Warren J Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:32
CPC Classifications
B; B65; B65G; B65G47/00; B65G47/34; B65G47/46; B65G47/48; B65G47/49; B65G47/493; G; G06; G06K; G06K7/00; G06K7/01; G06K7/016; G06K7/0163
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
240 words
A code detecting and control circuit for scanning a moving object having thereon a series of spaced clock pulse indicia and a related series of spaced code indicia which normally conform to a uniform standard width and a uniform standard spacing between standard width marks that exceeds the mark width, said code detecting and control circuit comprising first, second and third indicia detectors for producing output signals in response to indicia sense, said first and second indicia detectors being spaced apart in the direction of travel of the moving object by a distance greater than the width of a conforming clock pulse indicium and different than the space between any two clock pulse indicia and positioned to detect the clock pulse indicia in sequence as the object moves past each detector, said third indicia detector being positioned to detect in sequence the code indicia related to the clock pulse indicia at the time the clock pulse indicia is sensed by said first indicia detector, circuit means connected to said first, second and third indicia detector for registering code signals in binary number form representing the simultaneous occurrences and nonoccurrences of clock and code indiciums sensed by the first and third indicia detectors, and a clock pulse testing circuit connected to said first and second indicia detectors for simultaneously sensing the outputs thereof to produce a control signal if both outputs are of a predetermined sense at the time of sensing.
Claim 2
Dependent Claim
240 words
A code detecting and control circuit for scanning a moving object having thereon a series of spaced clock pulse indicia and a related series of spaced code indicia which normally conform to a uniform standard width and a uniform standard spacing between standard width marks that exceeds the mark width, said code detecting and control circuit comprising first, second and third indicia detectors for producing output signals in response to indicia sense, said first and second indicia detectors being spaced apart in the direction of travel of the moving object by a distance greater than the width of a conforming clock pulse indicium and different than the space between any two clock pulse indicia and positioned to detect the clock pulse indicia in sequence as the object moves past each detector, said third indicia detector being positioned to detect in sequence the code indicia related to the clock pulse indicia at the time the clock pulse indicia is sensed by said first indicia detector, circuit means connected to said first, second and third indicia detector for registering code signals in binary number form representing the simultaneous occurrences and nonoccurrences of clock and code indiciums sensed by the first and third indicia detectors, and a clock pulse testing circuit connected to said first and second indicia detectors for simultaneously sensing the outputs thereof to produce a control signal if both outputs are of a predetermined sense at the time of sensing.
Claim 3
Dependent Claim
69 words
A code detecting and control circuit as described in claim 1 wherein said first and second indicia detectors are spaced apart by a distance greater than the width of a conforming clock pulse indicium and less than a space between successive clock pulse indicia, and said clock pulse testing circuit produces a reject signal in response to both said first and second indicia detectors simultaneously sensing clock pulse indicia.
Claim 4
Dependent Claim
81 words
A code detecting and control circuit as described in claim 2 wherein said clock pulse testing circuit includes a time delay circuit that initiates a predetermined time delay period in response to both said first and second indicia detectors simultaneously sensing a space between clock pulse indicia, and said clock pulse testing circuit produces a reject signal after expiration of the time delay period if said first indicia detector fails to sense a clock pulse indicia during the time delay period.
Claim 5
Dependent Claim
59 words
A code detecting and control circuit as described in claim 1 wherein said first, second and third indicia detectors sense transition between indicia and spaces and said circuit means produces a reject signal responsive to said first and second indicia detectors sensing transitions from indicia to space and back to indicia without said third indicia detector sensing a space.
Claim 6
Dependent Claim
74 words
A code detecting and control circuit as described in claim 1 wherein said moving object includes identification indicia; said first, second and third indicia detectors sense transitions between indicia and spaces; and an identification circuit connected to said first, second and third indicia detectors for sensing sequentially transitions detected by each indicia detector and producing an enabling signal to said circuit means responsive to sensing a predetermined sequence of transitions representing an identification code.
Claim 7
Dependent Claim
67 words
A code detecting and control circuit as described in claim 5 wherein said first and second indicia detectors are spaced apart in the direction of travel of the moving object by a distance less than the width of an identification indicium, and said identIfication circuit resets without producing an enabling signal when the first indicia detector senses two transitions before the second indicia detector senses one transition.
Claim 8
Dependent Claim
52 words
A code detecting and control circuit as described in claim 5 wherein said first and third indicia detectors are spaced vertically in relationship to each other, and said identification circuit resets without producing an enabling signal when the first indicia detector senses two transitions before the third indicia detector senses one transition.
Claim 9
Dependent Claim
46 words
A code detecting and control circuit as described in claim 5 wherein said clock pulse testing circuit produces a reject signal in response to the first indicia detector sensing a clock pulse indicium at the same time that the second indicia detector senses an identification indicium.
Claim 10
Dependent Claim
39 words
A code detecting and control circuit as described in claim 1 including an error detection and correction circuit connected to said circuit means for checking the code signals registered in binary number form and correcting single signal errors therein.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-08 | 1974-08-10 | 1975-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-08 | 1978-08-10 | 1979-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-08 | 1982-08-10 | 1983-02-09 | $7700.00 | Window Closed / Lapsed |