Loading logic circuitry for deltic memory

Abstract

Abstract LOADING CIRCUITRY FOR THE ASYNCHRONOUS SAMPLING OF ANALOG INFORMATION AND THE INSERTION OF DATA PULSES SO DERIVED INTO A DELTIC (DELAY LINE TIME COMPRESSOR) MEMORY HAVING A GIVEN DATA RECIRCULATION PERIOD AND A RECIRCULATION RATE FIXED BY AN INTERNAL CLOCK FREQUENCY. THE ANALOG DATA IS PERIODICALLY SAMPLED AT ANY DESIRED RATE AND TIME COMPLETELY INDEPENDENTLY OF AND IN ASYNCHRONISM WITH THE GIVEN RECIRCULATION RATE OF THE DELTIC MEMORY. SUBSEQUENT TO EACH ASYNCHRONOUS SAMPLING OPERATION, THE DATA PULSE SO PROVIDED IS THEN SYNCHRONIZED WITH RESPECT TO THE INTERNAL CLOCK OF THE DELTIC MEMORY, STORED, AND INSERTED INTO THE DELTIC MEMORY RECIRCULATION LOOP AT A PROPER TIME INTERVAL. THE LOADING CIRCUITRY OF THE INSTANT INVENTION ACCORDINGLY ALLOWS EXTERNAL ANALOG DATA TO BE SAMPLED AT VIRTUALLY ANY TIME AND AT ANY RATE UP TO TWICE THE RECIRCULATION RATE OF THE DELTIC MEMORY IN A MANNER COMPLETELY INDEPENDENT FROM THE RECIRCULATION RATE OF THE DELTIC MEMORY, THUS INCREASING THE UTILITY OF A DELTIC SYSTEM. YET, THE LOADING CIRCUITY OF THE INSTANT INVENTION ENSURES THAT THE ACTUAL INSERTION OF THE THUS SAMPLED DATA TAKES PLACE AT THE DESIRED TIME INTERVAL OF THE RECIRCULATION PERIOD.

Inventors

• 👤 Francis C Martin Jr

Bibliographic Details