US3555260A
Expired / Lapsed
US
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Chromatogram analyzer
Assignee: Applied Biosystems Inc
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Filing: 1968-03-04
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Granted: 1971-01-12
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Expires: 1988-03-04
Abstract
Abstract A chromatogram analyzer is provided which continuously computes successive digital sums A of pulses derived from an analogue to digital converter, each sum being representative of the average amplitude of an analogue input signal during N successive intervals of time Delta tc. Successively generated sums A, formed during a prior period of time T, are stored and from this data the average rate of change of slope B'' of the signal baseline component is calculated. The amplitude of a sum occurring next in time is predicted from this data and is compared with the sum Ao as actually measured. A difference in amplitude existing between Ao and the predicted baseline value Bp is compared with preestablished criteria PC for sensing and indicating the beginning of a signal peak and the existence of a valley between unresolved peaks. A difference in amplitude Is existing between and is compared for sensing and indicating peak tops and termination of peak. Upon sensing the initiation of a peak, the difference between predicted baseline Bp and actual sum Ao is accumulated for each of the intervals N of the peak. A highly accurate baseline corrected peak integration is thereby provided.
Inventors
- 👤 Jimmy G Karohl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:57
CPC Classifications
G; G01; G01N; G01N30/00; G01N30/02; G01N30/86; G01N30/8624; G01N30/8641; G06; G06F; G06F2218/00; G06F2218/08; G06F2218/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
227 words
A chromatogram analyzer for providing an integral of an area under a peak of a chromatogram corrected for variations in amplitude of a baseline component, comprising: an analog-to-digital converter circuit arrangement for converting the amplitude of an electrical analogue signal into electrical digital representations; a digital counter coupled to said converter for counting said digital representations to provide the sum Sc of said dIgital representations during equal intervals of time incrementtc; an electrical memory storage means having a plurality of memory locations for storing information in the form of electrical signals applied thereto; arithmetic circuit means coupled to said digital counter and to said storage means for operating on two successive input signals for forming a resultant sum or difference thereof in accordance with a control signal applied thereto; means providing and coupling to said arithmetic means a signal PC in digital form having a characteristic indicative of the initiation of a peak; and control circuit means coupled to said counter means and to said arithmetic means for controlling the operation of said counter and arithmetic means to thereby compare successive groups of digital resultants where each group comprises a sum of digital representations occurring during N intervals of time incrementtc, said control means forming a difference between successive groups, and summing said differences when said differences exceed the peak criteria characteristic represented by said signal PC.
Claim 2
Dependent Claim
227 words
A chromatogram analyzer for providing an integral of an area under a peak of a chromatogram corrected for variations in amplitude of a baseline component, comprising: an analog-to-digital converter circuit arrangement for converting the amplitude of an electrical analogue signal into electrical digital representations; a digital counter coupled to said converter for counting said digital representations to provide the sum Sc of said dIgital representations during equal intervals of time incrementtc; an electrical memory storage means having a plurality of memory locations for storing information in the form of electrical signals applied thereto; arithmetic circuit means coupled to said digital counter and to said storage means for operating on two successive input signals for forming a resultant sum or difference thereof in accordance with a control signal applied thereto; means providing and coupling to said arithmetic means a signal PC in digital form having a characteristic indicative of the initiation of a peak; and control circuit means coupled to said counter means and to said arithmetic means for controlling the operation of said counter and arithmetic means to thereby compare successive groups of digital resultants where each group comprises a sum of digital representations occurring during N intervals of time incrementtc, said control means forming a difference between successive groups, and summing said differences when said differences exceed the peak criteria characteristic represented by said signal PC.
Claim 3
Dependent Claim
37 words
The apparatus of claim 1 wherein said arithmetic circuit means under the control of said control circuit means compares groups of digital representations, each group of digital representations occurring in N Incrementtc intervals of time, where N>0.
Claim 4
Dependent Claim
211 words
Signal interpreting apparatus for operating on an analogue signal having a baseline component subject to amplitude variation and a peak component extending from the baseline component to provide a baseline corrected integral of the area under a peak, comprising: an analogue-to-digital converter for converting the amplitude of the analogue signal into digital representations; an electrical counter coupled to said converter for accumulating the digital representations occurring during successive intervals of time Incrementtc; electrical arithmetic means adapted for operating on first and second input signals to provide a sum or difference thereof in accordance with a control signal applied thereto; an electrical digital storage means having a plurality of memory locations; means for establishing a peak slope criteria in electrical digital form which is representative of a characteristic of a peak; and means comprising a plurality of logical gates for defining a plurality of different operational states coupling said counter and storage means to said arithmetic means, and said slope criteria means to said arithmetic means to thereby form a difference between successively occurring groups, each group representative of the sum of digital representations occurring during a number N of intervals Incrementtc, and for periodically comparing the difference with said peak criteria, and for summing said differences when the criteria is satisfied.
Claim 5
Dependent Claim
211 words
Signal interpreting apparatus for operating on an analogue signal having a baseline component subject to amplitude variation and a peak component extending from the baseline component to provide a baseline corrected integral of the area under a peak, comprising: an analogue-to-digital converter for converting the amplitude of the analogue signal into digital representations; an electrical counter coupled to said converter for accumulating the digital representations occurring during successive intervals of time Incrementtc; electrical arithmetic means adapted for operating on first and second input signals to provide a sum or difference thereof in accordance with a control signal applied thereto; an electrical digital storage means having a plurality of memory locations; means for establishing a peak slope criteria in electrical digital form which is representative of a characteristic of a peak; and means comprising a plurality of logical gates for defining a plurality of different operational states coupling said counter and storage means to said arithmetic means, and said slope criteria means to said arithmetic means to thereby form a difference between successively occurring groups, each group representative of the sum of digital representations occurring during a number N of intervals Incrementtc, and for periodically comparing the difference with said peak criteria, and for summing said differences when the criteria is satisfied.
Claim 6
Dependent Claim
38 words
The apparatus of claim 3 wherein said operational states include a peak sensing mode and a peak accumulating mode, said criteria defines the initiation of a peak, and said differences are summed during the occurrence of a peak.
References Cited (Backward Citations)
US3284616A
Cited
US3412241A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-11 | 1974-07-13 | 1975-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-11 | 1978-07-13 | 1979-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-11 | 1982-07-13 | 1983-01-12 | $7700.00 | Window Closed / Lapsed |