Method of forming a semiconductor integrated circuit that includes a fast switching transistor

Claim 1

IN A METHOD OF FORMING A SEMICONDUCTOR INTEGRATED CIRCUIT THAT INCLUDES AT LEAST ONE FAST SWITCHING TRANSISTOR, THE STEPS COMPRISING: FORMING IN P-N JUNCTION RELATION WITH A SURFACE OF A SUBSTRATE OF A FIRST TYPE OF SEMICONDUCTIVITY A REGION OF A SECOND TYPE OF SEMICONDUCTIVITY; FORMING AN EPITAXIAL LAYER OF SAID SECOND TYPE OF SEMICONDUCTIVITY ON SAID SURFACE COVERING SAID REGION, SAID LAYER HAVING A RESISTIVITY SUBSTANTIALLY GREATER THAN THAT OF SAID REGION; DEPOSITING A FIRST QUANTITY OF DOPING IMPURITY CAPABLE OF IMPARTING SAID FIRST TYPE OF SEMICONDUCTIVITY ON A SURFACE OF SAID LAYER IN A PATTERN FOR ISOLATING FUNCTIONAL ELEMENTS OF THE INTEGRATED CIRCUIT; DEPOSITING A SECOND QUANTITY OF DOPING IMPURITY CAPABLE OF IMPARTING SAID FIRST TYPE OF SEMICONDUCTIVITY ON SAID SURFACE IN A FIRST ISOLATED PORTION HEREOF, SAID FIRST QUANTITY AMOUNTING TO A SUBSTANTIALLY GREATER CONCENTRATION OF DOPING IMPURITY PER UNIT AREA THAN SAID SECOND QUANTITY; DEPOSITING A THIRD QUANTITY OF DOPING IMPURITY CAPABLE OF IMPARTING SAID SECOND TYPE OF SEMICONDUCTIVITY IN A PATTERN SURROUNDING SAID SECOND QUANTITY OF DOPING IMPURITY; HEATING THE STRUCTURE TO DRIVE SIMULTANEOUSLY SAID FIRST AND THIRD QUANTITIES OF DOPING IMPURITY THROUGH SAID LAYER TO FORM AN ISOLATION WALL AND A COLLECTOR WALL, RESPECTIVELY, AND SAID SECOND QUANTITY OF DOPING IMPURITY TO A POSITION WITHIN SAID LAYER TO FORM A TRANSISTOR BASE REGION, FORMING AN ADDITIONAL REGION OF SAID SECOND TYPE OF SEMICONDUCTIVITY IN SAID BASE REGION TO SERVE AS AN EMITTER REGION; AND FORMING OHMIC CONTACTS AT LEAST TO SAID COLLECTOR WALL AND SAID BASE AND EMITTER REGIONS.