Split-phase code modulation synchonizer and translator

Claim 2

A SYNCHRONIZER CIRCUIT FOR GENERATING CLOCK PULSE SIGNALS IN RESPONSE TO AND SYNCHRONIZED WITH A SPLIT-PHASE PULSE CODE MODULATED INPUT SIGNAL, COMPRISING: INPUT MEANS RESPONSIVE TO SAID SPLIT-PHASE PULSE CODE MODULATED INPUT SIGNAL; MEANS COUPLED TO SAID INPUT MEANS FOR DIFFERENTIATING SAID INPUT SIGNAL TO PROVIDE A SERIES OF POSITIVE AND NEGATIVE GOING VOLTAGE SPIKES SYNCHRONIZED WITH THE TRANSITIONS OF SAID INPUT SIGNAL; MEANS RESPONSIVE TO SAID VOLTAGE SPIKES FOR PROVIDING A SQUARE WAVE SIGNAL WHOSE FREQUENCY IS DETERMINED BY THE MINIMUM SPACING BETWEEN SAID VOLTAGE SPIKES; AND MEANS COUPLED TO SAID LAST-MENTIONED MEANS FOR DIVIDING SAID SQUARE WAVE FREQUENCY BY TWO TO PROVIDE SAID CLOCK PULSE SIGNALS.

Claim 3

A SYNCHRONIZER CIRCUIT FOR GENERATING CLOCK PULSE SIGNALS IN RESPONSE TO AND SYNCHRONIZED WITH A SPLITPHASE PULSE CODE MODULATED INPUT SIGNAL, COMPRISING: INPUT MEANS RESPONSIVE TO SAID INPUT SIGNAL; FILTER MEANS COUPLED TO SAID INPUT MEANS FOR PASSING THE FUNDAMENTAL SINUSOIDAL COMPONENT OF SAID INPUT SIGNAL; MEANS FOR PROVIDING A SINUSOIDAL SIGNAL WHOSE FREQUENCY IS DETERMINED BY A CONTROL SIGNAL; MEANS FOR COMPARING THE PHASE OF SAID FUNDAMENTAL SINUSOIDAL COMPONENT WITH THE PHASE OF SAID SINUSOIDAL SIGNAL TO PROVIDE SAID CONTROL SIGNAL; MEANS RESPONSIVE TO SAID SINUSOIDAL SIGNAL FOR PROVIDING A SQUARE WAVE SIGNAL WHOSE FREQUENCY EQUALS THE FREQUENCY OF SAID SINUSOIDAL SIGNAL; AND MEANS COUPLED TO SAID LAST-MENTIONED MEANS FOR DIVIDING SAID SQUARE WAVE SIGNAL FREQUENCY BY TWO TO PROVIDE SIDE CLOCK PULSE SIGNALS.

Claim 4

A SYNCHRONIZER CIRCUIT FOR GENERATING CLOCK PULSE SIGNALS IN RESPONSE TO AND SYNCHRONIZED WITH A SPLITPHASE PULSE CODE MODULATED INPUT SIGNAL, COMPRISING: INPUT MEANS RESPONSIVE TO SAID INPUT SIGNAL; FILTER MEANS COUPLED TO SAID INPUT MEANS FOR PASSING THE FUNDAMENTAL SINUSOIDAL COMPONENT OF SAID INPUT SIGNAL; MEANS FOR PROVIDING A SINUSOIDAL SIGNAL WHOSE FREQUENCY IS DETERMINED BY A CONTROL SIGNAL; MEANS FOR COMPARING THE PHASE OF SAID FUNDAMENTAL SINUSOIDAL COMPONENT WITH THE PHASE OF SAID SINUSOIDAL SIGNAL TO PROVIDE SAID CONTROL SIGNAL; MEANS RESPONSIVE TO SAID SINUSOIDAL SIGNAL FOR PROVIDING A SQUARE WAVE SIGNAL WHOSE FREQUENCY EQUALS THE FREQUENCY OF SAID SINUSOIDAL SIGNAL; AND MEANS COUPLED TO SAID LAST-MENTIONED MEANS FOR DIVIDING SAID SQUARE WAVE SIGNAL FREQUENCY BY TWO TO PROVIDE SIDE CLOCK PULSE SIGNALS.

Claim 5

A SYNCHRONIZER CIRCUIT FOR GENERATING CLOCK PULSE SIGNALS IN RESPONSE TO AND SYNCHRONIZED WITH A SPLIT-PHASE PULSE CODE MODULATED INPUT SIGNAL, SAID INPUT SIGNAL CONTAINING BINARY INFORMATION IN A SEQUENCE OF BIT TIME PERIODS, EACH OF SAID BIT TIME PERIODS CONTAINING A BILEVEL SIGNAL WHICH REPRESENTS A BINARY 1 OR A BINARY 0, SAID SYNCHRONIZER CIRCUIT COMPRISING: MEANS FOR RECEIVING SAID SPLIT-PHASE PULSE CODE MODULATED INPUT SIGNAL; MEANS COUPLED TO SAID RECEIVING MEANS FOR GENERATING FIRST AND SECOND PULSE TRAINS, EACH OF SAID PULSE TRAINS BEING EQUAL IN FREQUENCY TO THE RECIPROCAL OF SAID BIT TIME PERIOD BUT BEING 180* OUT OF PHASE WITH EACH OTHER; FIRST INTEGRATING MEANS COUPLED TO SAID RECEIVING MEANS AND RESPONSIVE TO SAID FIRST PULSE TRAIN FOR REPEATEDLY INTEGRATING SAID INPUT SIGNAL OVER AN INTEGRATING INTERVAL WHICH EQUALS THE PERIOD OF SAID FIRST PULSE TRAIN; SECOND INTEGRATING MEANS COUPLED TO SAID RECEIVING MEANS AND RESPONSIVE TO SAID SECOND PULSE TRAIN FOR REPEATEDLY INTEGRATING SAID INPUT SIGNAL OVER AN INTEGRATING INTERVAL WHICH EQUALS THE PERIOD OF SAID SECOND PULSE TRAIN; MEANS FOR COMPARING THE OUTPUTS OF SAID FIRST AND SECOND INTEGRATING MEANS OVER A PLURALITY OF BIT TIME PERIODS TO DETERMINE WHICH OF SAID FIRST AND SECOND INTEGRATING MEANS PRODUCES THE SMALLER NUMBER OF NON-ZERO INTEGRALS OVER SAID PLURALITY OF BIT TIMER PERIODS; AND MEANS RESPONSIVE TO SAID MEANS FOR COMPARING FOR SELECTING THE PULSE TRAIN YIELDING THE SMALLER NUMBER OF NON-ZERO INTEGRALS AS THE CLOCK PULSE SIGNAL.

Claim 6

A SYNCHRONIZER CIRCUIT FOR GENERATING CLOCK PULSE SIGNALS IN RESPONSE TO AND SYNCHRONIZED WITH A SPLIT-PHASE PULSE CODE MODULATED INPUT SIGNAL, SAID INPUT SIGNAL CONTAINING BINARY INFORMATION IN A SEQUENCE OF BIT TIME PERIODS, EACH OF SAID BIT TIME PERIODS CONTAINING A BILEVEL SIGNAL WHICH REPRESENTS A BINARY 1 OR A BINARY 0, SAID SYNCHRONIZER CIRCUIT COMPRISING: MEANS FOR RECEIVING SAID SPLIT-PHASE PULSE CODE MODULATED INPUT SIGNAL; MEANS COUPLED TO SAID RECEIVING MEANS FOR GENERATING FIRST AND SECOND PULSE TRAINS, EACH OF SAID PULSE TRAINS BEING EQUAL IN FREQUENCY TO THE RECIPROCAL OF SAID BIT TIME PERIOD BUT BEING 180* OUT OF PHASE WITH EACH OTHER; FIRST INTEGRATING MEANS COUPLED TO SAID RECEIVING MEANS AND RESPONSIVE TO SAID FIRST PULSE TRAIN FOR REPEATEDLY INTEGRATING SAID INPUT SIGNAL OVER AN INTEGRATING INTERVAL WHICH EQUALS THE PERIOD OF SAID FIRST PULSE TRAIN; SECOND INTEGRATING MEANS COUPLED TO SAID RECEIVING MEANS AND RESPONSIVE TO SAID SECOND PULSE TRAIN FOR REPEATEDLY INTEGRATING SAID INPUT SIGNAL OVER AN INTEGRATING INTERVAL WHICH EQUALS THE PERIOD OF SAID SECOND PULSE TRAIN; MEANS FOR COMPARING THE OUTPUTS OF SAID FIRST AND SECOND INTEGRATING MEANS OVER A PLURALITY OF BIT TIME PERIODS TO DETERMINE WHICH OF SAID FIRST AND SECOND INTEGRATING MEANS PRODUCES THE SMALLER NUMBER OF NON-ZERO INTEGRALS OVER SAID PLURALITY OF BIT TIMER PERIODS; AND MEANS RESPONSIVE TO SAID MEANS FOR COMPARING FOR SELECTING THE PULSE TRAIN YIELDING THE SMALLER NUMBER OF NON-ZERO INTEGRALS AS THE CLOCK PULSE SIGNAL.