Common series double comparison circuit for a time division multiplex system

Claim 1

A COMMON SERIES DOUBLE COMPARISON CIRCUIT COMPRISING A BINARY BIT SOURCE FOR PRODUCING AT A PREDETERMINED BIT RATE A SINGLE SERIAL STREAM OF INDIVIDUAL BINARY BITS EACH OF WHICH BITS MANIFESTS EXCLUSIVELY EITHER A BINARY ONE OR A BINARY ZERO, SAID STREAM COMPRISING AT LEAST ONE TIME SET EACH OF WHICH CONSISTS OF 3N CONSECUTIVE BITS, N BEING A PLURAL INTEGER, WHEHEIN THE FIRST-OCCURRING N CONSECUTIVE BITS OF EACH TIME SET MANIFESTS A FIRST CHARACTER THEREOF, THE SECOND-OCCURRING N CONSECUTIVE BITS OF EACH TIME SET MANIFESTS A PREDETERMINED CHARACTER THEREOF AND THE THIRDOCCURRING N CONSECUTIVE BITS OF EACH TIME SET MANIFESTS A SECOND CHARACTER THEREOF; AND A COMMON SERIES COMPARISON CIRCUIT COUPLED TO SAID SOURCE AND RESPONSIVE TO THE OUTPUT THEREFROM FROM COMPARING SAID PREDETERMINED CHARACTER WITH EACH OF SAID FIRST AND SECOND CHARACTERS BIT BY BIT INCLUDING MEANS FOR PRODUCING AN OUTPUT SIGNAL IN RESPONSE TO EITHER SAID FIRST OR SECOND CHARACTERS BEING IDENTICAL TO SAID PREDETERMINED CHARACTER, A DELAY MEANS FOR REPRODUCING AT ITS OUTPUT A BIT APPLIED TO ITS INPUT AFTER A TIME DELAY EQUAL TO N BIT PERIODS, MEANS FOR APPLYING THE OUTPUT OF SAID SOURCE TO THE INPUT OF SAID DELAY MEANS, SAID COMPARISON CIRCUIT COMPRISING CONTROLLED FIRST BINARY LOGIC MEANS FOR PRODUCING AN OUTPUT WHEN ENABLED SOLELY IN RESPONSE TO EITHER A BIT MANIFESTING A BINARY ONE BEING APPLIED TO A FIRST INPUT THEREOF AND A BIT MANIFESTING A ZERO BEING SIMULTANEOUSLY APPLIED TO A SECOND INPUT THEREOF OR A BIT MANIFESTING A BINARY ZERO BEING APPLIED TO SAID FIRST INPUT THEREOF AND A BIT MANIFESTING A BINARY ONE BEING SIMULTANEOUSLY APPLIED TO SAID SECOND INPUT THEREOF, A BISTABLE SWITCH HAVING A SET CONDITION AND A RESET CONDITION, MEANS FOR APPLYING THE OUTPUT OF SAID FIRST BINARY LOGIC MEANS TO SAID BISTABLE SWITCH TO EFFECT THE SWITCHING THEREOF FROM A RESET CONDITION TO A SET CONDITION IN RESPONSE THERETO, CONTROLLED SECOND BINARY LOGIC MEANS COUPLED TO SAID BISTABLE SWITCH FOR PRODUCING AN OUTPUT WHEN ENABLED SOLELY IN REPONSE TO SAID SWITCH BEING IN ITS RESET CONDITION AND EITHER A BIT MANIFESTING A BINARY ONE BEING APPLIED TO A FIRST INPUT THEREOF AND A BIT MANIFESTING A BINARY ONE BEING ONE BEING SIMULTANEOUSLY APPLIED TO A SECOND INPUT THEREOF OR A BIT MANIFESTING A BINARY ZERO BEING APPLIED TO SAID FIRST INPUT THEREOF AND A BIT MANIFESTING A BINARY ZERO BEING SIMULTANEOUSLY APPLIED TO SAID SECOND INPUT THEREOF, MEANS FOR SIMULTANEOUSLY APPLYING THE BINARY BITS APPEARING AT THE INPUT OF SAID DELAY MEANS AS SAID FIRST INPUT TO BOTH SAID FIRST AND SECOND BINARY LOGIC MEANS AND THE BINARY BITS APPEARING AT THE OUTPUT OF SAID DELAY MEANS AS SAID SECOND INPUT TO BOTH SAID FIRST AND SECOND BINARY LOGIC MEANS, SYSTEM CONTROL MEANS INCLUDING FIRST CONTROL MEANS FOR DISABLING SAID FIRST BINARY LOGIC MEANS DURING THE TIME INTERVAL OF SAID TIME SET IN WHICH ALL BITS OF SAID FIRST CHARACTER ARE BEING APPLIED TO THE FIRST INPUT THEREOF AND FOR ENABLING SAID FIRST BINARY LOGIC MEANS AT LEAST DURING THE RESPECTIVE TIME INTERVALS OF SAID TIME SET IN WHICH THE FIRST (N-1) BITS OF SAID PREDETERMINED CHARACTER AND THE FIRST (N-1) BITS OF SAID SECOND CHARACTER ARE BEING APPLIED TO THE FIRST INPUT THEREOF, AND SECOND CONTROL MEANS FOR BOTH EFFECTING THE SWITCHING OF SAID BISTABLE SWITCH FROM A SET CONDITION THEREOF TO A RESET CONDITION THEREOF AND FOR ENABLING SAID SECOND BINARY LOGIC MEANS ONLY DURING THE RESPECTIVE TIME INTERVALS OF SAID TIME SET THAT SAID NTH BIT OF SAID PREDETERMINED AND SECOND CHARACTERS ARE BEING APPLIED TO THE FIRST INPUT THEREOF, WHEREBY AN OUTPUT FROM SAID SECOND BINARY LOGIC MEANS COMPRISES SAID COMPARISON CIRCUIT OUTPUT SIGNAL.