Multiline digital buffer

Claim 1

A MULTISTAGE DIFFERENTIAL DELAY NETWORK COMPRISING THREE STAGES, AN INPUT, AN OUTPUT, THREE SETS OF THREE "AND " GATES AND AN "OR" GATE HAVING CIRCUITS CONNECTED IN SERIES TO PROVIDE A DIRECT PATH BETWEEN SAID INPUT AND SAID OUTPUT, ONE SET FOR EACH STAGE, PLURALITY OF PAIRS OF DELAY LINE SECTIONS, TWO FOR EACH STAGE, AND "AND" GATE MEANS FOR INSERTING BETWEEN THE INPUTS AND OUTPUTS OF EACH OF THE STAGES, EITHER TWO OR ONE OF SAID DELAY LINE SECTIONS, THE TIME DELAY OF EACH OF THE DELAY LINE SECTION ASSOCIATED WITH THE THIRD STAGE BEING THREE TIMES AS LONG AS THE TIME DELAY OF EACH OF THE DELAY LINE SECTIONS ASSOCIATED WITH THE SECOND STAGE, AND THE TIME DELAY OF EACH OF THE DELAY LINE SECTIONS OF THE SECOND STAGE BEING THREE TIMES AS LONG AS THE TIME DELAY OF EACH OF THE DELAY LINE SECTIONS ASSOCIATED WITH THE FIRST STAGE, AND MEANS FOR CONTROLLING THE "AND" GATES ASSOCIATED WITH THE DELAY LINE SECTIONS SO AS TO IMPOSE ON THE SUCCESSIVE SAMPLES FROM ANY GIVEN SOURCE INCREMENTALLY DIMINISHED DELAYS.