Minority logical operator

Claim 1

A LOGIC ASSEMBLY WITH TWO GATING CIRCUITS FOR LOGIC OPERATIONS, SAID ASSEMBLY COMPRISING A FIRST GATING CIRCUIT HAVING THREE INPUT TERMINALS AND A SINGLE OUTPUT TERMINAL, TWO COMPLEMENTARY TRANSISTORS EACH HAVING A BASE, AN EMITTER AND A COLLECTOR, THE BASES OF BOTH SAID TRANSISTORS BEING CONNECTED TO SAID INPUT TERMINALS, THE EMITTERS OF SAID TRANSISTORS BEING AT A COMMON GROUND POTENTIAL, AND RESPECTIVE LOADS CONNECTING EACH OF SAID COLLECTORS TO THE OUTPUT TERMINAL OF SAID FIRST GATING CIRCUIT; A SECOND GATING CIRCUIT HAVING FIVE INPUT TERMINALS AND A SINGLE OUTPUT TERMINAL CONSTITUTING THE OUTPUT OF THE ASSEMBLY, TWO COMPLEMENTARY TRANSISTORS EACH HAVING A BASE, AN EMITTER AND A COLLECTOR, THE BASES OF BOTH TRANSISTORS OF SAID SECOND GATING CIRCUIT BEING CONNECTED TO THE INPUT TERMINALS OF SAID SECOND CIRCUIT, THE EMITTERS OF SAID TRANSISTORS OF SAID SECOND CIRCUIT BEING AT A COMMON GROUND POTENTIAL, AND RESPECTIVE LOADS CONNECTING EACH OF THE COLLECTORS OF SAID SECOND GATING CIRCUIT WITH THE OUTPUT TERMINAL THEREOF; AND MEANS FOR APPLYING VARIABLE FUNCTIONS AND AT LEAST ONE PARAMETER IN THE FORM OF ELECTRIC SIGNALS REPRESENTING THE LOGIC VALUES "0" AND "1" SELECTIVELY TO THE INPUT TERMINALS OF SAID FIRST GATING CIRCUIT, FOR CONNECTING THE OUTPUT TERMINAL OF SAID FIRST GATING CIRCUIT WITH TWO OF THE INPUT TERMINALS OF SAID SECOND GATING CIRCUIT, AND FOR APPLYING SAID VARIABLE FUNCTIONS AND A SECOND PARAMETER TO THE OTHER THREE INPUT TERMINALS OF SAID SECOND GATING CIRCUIT WHEREBY THE OUTPUT TERMINAL OF SAID SECOND GATING CIRCUIT DELIVERS ELECTRICAL SIGNALS REPRESENTING THE LOGIC VALUES "0" AND "1" IN ACCORDANCE WITH THE VALUES OF SAID PARAMETERS AND SAID VARIABLE FUNCTIONS.