Quadrature rejection circuit utilizing bilateral transistor gate

Claim 1

A QUADRATURE REJECTION CIRCUIT, COMPRISING: MEANS FOR PROVIDING AN INPUT SIGNAL, SAID INPUT SIGNAL HAVING AN INPHASE COMPONENT AND A COMPONENT IN QUADRATURE WITH THE INPHASE COMPONENT; SIGNAL GENERATING MEANS FOR PROVIDING A SIGNAL HAVING A SUBSTANTIALLY SQUARE WAVEFORM WITH A PREDETERMINED RISE AND FALL TIME; A GATE COMPRISING FIRST AND SECOND BILATERAL TRANSISTORS EACH OF WHICH HAS A BASE, A FIRST EMITTER AND A SECOND EMITTER; MEANS INCLUDING A RESISTOR AND A CAPACITOR CONNECTED IN SERIES, SAID MEANS BEING CONNECTED TO THE SECOND EMITTER OF THE FIRST BILATERAL TRANSISTOR AND TO THE INPUT SIGNAL MEANS FOR APPLYING THE INPUT SIGNAL TO THE GATE; THE BASE AND THE FIRST EMITTER OF EACH OF THE FIRST AND SECOND BILATERAL TRANSISTORS BEING CONNECTED TO THE SIGNAL GENERATING MEANS SO THAT THE GATE IS OPENED BY THE SIGNAL THEREFROM FOR PROVIDING AT THE SECOND EMITTER OF THE SECOND TRANSISTOR THE INPHASE COMPONENT OF THE INPUT SIGNAL, AND THE GATE BEING CLOSED BY THE SIGNAL FROM THE SIGNAL GENERATING MEANS FOR PREVENTING SAID QUADRATURE COMPONENT OF SAID INPUT SIGNAL FROM BEING PROVIDED AT THE SECOND EMITTER OF THE SECOND TRANSISTOR; AND MEANS CONNECTED TO THE SECOND EMITTER OF THE SECOND TRANSISTOR AND RESPONSIVE TO THE SIGNAL THEREAT FOR PROVIDING A SIGNAL PROPORTIONAL TO THE AMPLITUDE OF THE INPHASE COMPONENT.