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US3290661A Expired / Lapsed US ⏱️ 0.0 years remaining

Content addressable associative memory with an output comparator

Assignee: Unisys Corp
•
Filing: 1962-11-19
•
Granted: 1966-12-06
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Expires: 1982-11-19
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Abstract

No abstract record available.

Inventors

  • 👤 Francis J Belcourt
  • 👤 Louzelle A Luke

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 22:24
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/58; G; G11; G11C; G11C15/00; G11C15/04; H03K3/00; H03K3/02; H03K3/313; H03K3/315

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 164 words
APPARATUS OF THE NATURE DESCRIBED COMPRISING IN COMBINATION: N BISTABLE CIRCUITS EACH HAVING OPERATIONAL STATES OF RELATIVELY HIGH RELATIVELY LOW IMPEDANCE LEVELS; FIRST MEANS COUPLED TO ALL OF SAID CIRCUITS FOR SWITCHING THEM TO THE SAME FIST IMPEDANCE LEVEL; A GROUP OF N INPUT LINES EACH COUPLED TO A RESPECTIVELY DIFFERENT ONE OF THE BISTABLE CIRCUITS EACH OF SAID LINES BEING ASSOCIATED WITH A DIFFERENT ONE OF A PLURALITY OF MEMORY LOCATIONS RESPECTIVELY DESIGNATED 0 THROUGH N-1; MEANS FOR APPLYING INFORMATION-REPRESENTING BINARY SIGNALS TO SAID GROUP OF LINES FOR SWITCHING THE RESPECTIVELY CORRESPONDING BISTABLE CIRCUITS FROM SAID FIRST IMPEDANCE LEVEL TO THE OTHER IMPEDANCE LEVEL WHEN THE CORRESPONDING BINARY INPUT SIGNAL IS OF A FIRST BINARY VALUE; AN INTERROGATE LINE CONSTRUCTED TO EXPERIENCE TRANSMISSION LINE EFFECTS HAVING AN INPUT END AND A TERMINATING END; INPUT CIRCUIT MEANS COUPLING EACH OF SAID BISTABLE CIRCUITS IN PARALLEL TO ONE ANOTHER TO SAID INTERROGATE LINE IN SPACED REALTIONSHIP ALONG SAID LINE WITH THE BISTABLE CIRCUIT ASSOCIATED WITH
Claim 2
Dependent Claim 164 words
APPARATUS OF THE NATURE DESCRIBED COMPRISING IN COMBINATION: N BISTABLE CIRCUITS EACH HAVING OPERATIONAL STATES OF RELATIVELY HIGH RELATIVELY LOW IMPEDANCE LEVELS; FIRST MEANS COUPLED TO ALL OF SAID CIRCUITS FOR SWITCHING THEM TO THE SAME FIST IMPEDANCE LEVEL; A GROUP OF N INPUT LINES EACH COUPLED TO A RESPECTIVELY DIFFERENT ONE OF THE BISTABLE CIRCUITS EACH OF SAID LINES BEING ASSOCIATED WITH A DIFFERENT ONE OF A PLURALITY OF MEMORY LOCATIONS RESPECTIVELY DESIGNATED 0 THROUGH N-1; MEANS FOR APPLYING INFORMATION-REPRESENTING BINARY SIGNALS TO SAID GROUP OF LINES FOR SWITCHING THE RESPECTIVELY CORRESPONDING BISTABLE CIRCUITS FROM SAID FIRST IMPEDANCE LEVEL TO THE OTHER IMPEDANCE LEVEL WHEN THE CORRESPONDING BINARY INPUT SIGNAL IS OF A FIRST BINARY VALUE; AN INTERROGATE LINE CONSTRUCTED TO EXPERIENCE TRANSMISSION LINE EFFECTS HAVING AN INPUT END AND A TERMINATING END; INPUT CIRCUIT MEANS COUPLING EACH OF SAID BISTABLE CIRCUITS IN PARALLEL TO ONE ANOTHER TO SAID INTERROGATE LINE IN SPACED REALTIONSHIP ALONG SAID LINE WITH THE BISTABLE CIRCUIT ASSOCIATED WITH

References Cited (Backward Citations)

US3103597A Cited
US3089121A Cited
US3102255A Cited
US3115585A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1969-12-05 1970-06-06 1970-12-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1973-12-05 1974-06-06 1974-12-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1977-12-05 1978-06-06 1978-12-06 $7700.00 Window Closed / Lapsed

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