Information handling apparatus including time sharing of plural addressable peripheral device transfer channels

Claim 1

THE COMBINATION OF A DATA PROCESSOR, A PLURALITY OF PERIPHERAL DEVICE TRANSFER CHANNELS EACH COUPLED OVER A COMMON MULTI-CONDUCTOR SIGNAL BUS TO SAID DATA PROCESSOR, A TRANSFER CHANNEL PRIORITY SELECTOR AND CODER MEANS ASSOCIATED WITH SAID DATA PROCESSOR, OPERATIONAL READINESS INDICATING MEANS IN EACH TRANSFER CHANNEL COUPLED OVER RESPECTIVE "READY" LINES TO RESPECTIVE INPUTS OF SAID PRIORITY SELECTOR AND CODER MEANS, WHEREBY THE OUTPUT OF THE PRIORITY SELECTOR AND CODER MEANS IS A CODED NUMBER SIGNAL CORRESPONDING TO THE HIGHEST PRIORITY ONE OF THE TRANSFER CHANNELS PROVIDING AN INPUT TO THE SELECTOR AND CODER MEANS, AN INDIVIDUAL TRANSFER CHANNEL NUMBER SIGNAL DECODER CIRCUIT IN EACH TRANSFER CHANNEL, MEANS TO COUPLE SAID CODED NUMBER SIGNAL FROM SAID SELECTOR AND CODER MEANS OVER AN ADDRESS LINE TO THE NUMBER SIGNAL DECODER CIRCUITS IN ALL TRANSFER CHANNELS, AND GATE MEANS IN EACH TRANSFER CHANNEL RESPONSIVE TO THE DECODER CIRCUIT THEREIN TO CONDITION THE ADDRESSED TRANSFER CHANNEL FOR COMMUNICATION OVER THE SIGNAL BUS WITH THE DATA PROCESSOR.