Interference-free a.-c. switch

Claim 1

A SILICON-CONTROLLED GATED RECTIFIER SWITCHING SYSTEM COMPRISING: A SOURCE OF ALTERNATING CURRENT HAVING AT LEAST A CURRENT LEAD, AND A COMMON LEAD; A FIRST GATED SILICON-CONTROLLED RECTIFIER MEANS CONNECTED IN SERIES WITH SAID CURRENT LEAD AND POLED SO AS TO BE CONDUCTIVE, ONLY DURING THE CONCIDENCE OF A FIRST FORWARD-BIASING GATING SIGNAL AND THE POSITIVE HALF-CYCLES OF THE ALTERNATING CURRENT IN SAID SOURCE; A SECOND GATED SILICON-CONTROLLED RECTIFIER MEANS CONNECTED IN PARALLEL WITH SAID FIRST GATED SILICON-CONTROLLED RECTIFIER MEANS AND POLED SO AS TO BE CONDUCTIVE ONLY DURING THE COINCIDENCE OF SECOND FORWARDBIASING GATING SIGNAL AND THE NEGATIVE HALF-CYCLES OF THE ALTERNATING CURRENT IN SAID SOURCE; PHASE-INVERTING MEANS COUPLED TO SAID SOURCE FOR DEVELOPING ALTERNATING-CURRENT SIGNALS WHICH ARE OPPOSITE IN PHASE WITH RESPECT TO SAID SOURCE; FIRST FORWARD-BIASING-SIGNAL GENERATING MEANS CONNECTED TO SAID PHASE INVERTING MEANS IN SUCH POLARITY AS TO PRODUCE A FIRST POSITIVE DIRECT-CURRENT GATING POTENTIAL ON THE HALF-CYCLE OF THE ALTERNATING CURRENT IN SAID PHASE-INVERTING MEANS CORESPONDING TO NEGATIVE HALFCYCLES OF SAID SOURCE, SAID FIRT FORWARD-BIASING SIGNAL GENERATING MEANS BEING CONNECTED TO SAID FIRST GATED SILICON-CONTROLLED RECTIFIER; SECOND FORWARD-BIASING-SIGNAL GENERATING MEANS CONNECTED TO SAID PHASE-INVERTING MENS IN SUCH POLARITY AS TO PRODUCE A SECOND POSITIVE DIRECT-CURRENT GATING POTENTIAL ON A HALF-CYCLE OF THE ALTERNATING CURRENT IN SAID PHASE-INVERTING MEANS CORRESPONDING TO THE POSITIVE HALF-CYCLE IN SAID SOURCE, SAID SECOND FORWARD-BIASING-SIGNAL GENERATING MEANS BEING CONNECTED TO SAID SECOND GATED SILICON-CONTROLLED RECTIFIER; AND, A LOAD DEVICE BEING CONNECTED BETWEEN SAID PARALLEL CONNECTION OF SAID SILICON-CONTROLLED RECTIFIERS AND SAID COMMON LEAD OF SAID ALTERNATING-CURRENT SOURCE, WHEREBY WHEN ALTERNATING CURRENT FROM SAID SOURCE IS APPLIED TO SAID PHASE-INVERTING MEANS SAID FIRST GATING POTENTIAL IS APPLIED TO SAID FIRST GATED SILICONCONTROLLED RECTIFIER WHICH DOES NOT CONDUCT UNTIL CONTROLLED RECTIFIER WHICH DOES NOT CONDUCT UNTIL A SUCCEEDING POSITIVE HALF CYCLE OF SAID SOURCE WHEREUPON CONDUCTION OF SAID FIRST SILICON-CONTROLLED RECTIFIER OCCURS BEGINNING AT THE INITIATION OF SAID SUCCEEDING POSITIVE HALF-CYCLE OF SAID SOURCE AND ON SUCCEEDING POSITIVE HALF-CYCLES THEREAFTER, AND SAID SECOND GATING POTENTIAL IS APPLIED TO SAID SECOND GATED SILICON-CONTROLLED RECTIFIER WHICH DOES NOT CONDUCT UNTIL THERE IS COINCIDENCE OF SAID SECOND GATING POTENTIAL WITH A NEXT-FOLLOWING NEGATIVE HALF-CYCLE OF SAID ALTERNATING-CURRENT SOURCE WHEREUPON CONDUCTION OF SAID SECOND SILICON-CONTROLLED RECTIFIER OCCURS BEGINNING AT THE INITIATION OF SAID NEXT-FOLLOWING NEGATIVE HALF-CYCLE OF SAID ALTERNATING-CURRENT SOURCE AND ON NEGATIVE HALF-CYCLES OF SAID SOURCE FOLLOWING THEREAFTER, SO THAT ALTERNATING CURRENT FROM SAID SOURCE MAY BE APPLIED TO SAID LOAD, AND WHEN SAID ALTERNATING CURRENT FROM SAID SOURCE IS REMOVED FROM SAID PHASE-INVERTING MEANS SAID FIRST SILICON-CONTROLLED RECTIFIER WILL NO LONGER CONDUCT AT THE BEGINNING OF THE FIRST NEGATIVE HALF-CYCLE THEREAFTER, AT WHICH SAID COINCIDENCE IS NOT PRESENT, AND SAID SECONE SILICON-CONTROLLED RECTIFIER WILL NO LONGER CONDUCT AT THE BEGINNING OF THE FIRST POSITIVE HALF-CYCLE THEREAFTER, AT WHICH SAID COINCIDENCE IS NOT PRESENT, THEREBY REMOVING SAID ALTERNATING CURRENT FROM SAID LOAD, SAID APPLICATION OF SAID ALTERNATING CURRENT THEREBY TO SAID LOAD OCCURRING ON THE RISE OF A POSITIVE OR NEGATIVE HALF-CYCLE WITHOUT SUDDEN CHANGE AND THE REMOVAL OF SAID ALTERNATING CURRENT FROM SAID LOAD OCCURRING ON THE FALL OF A HLF-CYCLE WITHOUT SUDDEN CHANGE, SO AS TO ELIMINATE HIGH-FREQUENCY INTERFERENCE PRODUCING TRANSIENTS.