Nand nor logic circuit for use in a binary comparator

Claim 1

A NAND-NOR LOGIC GATE COMPRISING A PAIR OF COUPLING TRANSISTORS EACH HAVING A PLURALITY OF EMITTERS, A COLLECTOR AND A BASE; A SEPARATE RESISTOR CONNECTED TO THE BASE OF EACH OF SAID COUPLING TRANSISTORS, AN INVERTER TRANSISTOR HAVING AN EMITTER, COLLECTOR AND BASE, THE BASE OF SAID INVERTER TRANSISTOR BEING COUPLED TO THE COLLECTOR OF EACH OF SAID COUPLING TRANSISTORS; AND MEANS IN THE COUPLING BETWEEN THE BASE OF THE INVERTER TRANSISTOR AND EACH OF THE COLLECTORS OF THE COUPLING TRANSISTORS FOR PROVIDING A SUITABLE POTENTIAL DIFFERENCE TO INSURE THAT THE INVERTER TRANSISTOR IS OFF WHEN THE COUPLING TRANSISTORS ARE CONDUCTING BETWEEN THEIR BASE AND EMITTERS; THE EMITTERS OF THE COUPLING TRANSISTORS BEING THE INPUT TERMINALS OF THE GATE, AND THE COLLECTOR OF THE INVERTER TRANSISTOR BEING THE OUTPUT TERMINAL OF THE GATE.