Solid state sequencing and timing circuit

Claim 1

IN A RESISTANT WELDER CONTROL, THE COMBINATION COMPRISING; A SINGLE TIMER INCLUDING A NOR MEMORY AND A TIMING CAPACITOR ARRANGED FOR SUPPLYING A SWITCHING SIGNAL TO THE MEMORY WHENEVER A CHARGE ON THE CAPACITOR EXCEEDS A PREDETERMINED VALUE AND INCLUDING MEANS FOR DISCHARGING THE CAPACITOR AND RESETTING THE MEMORY IN RESPONSE TO A RESET SIGNAL, SAID TIMER ALSO HAVING AN OUTPUT TERMINAL IN CIRCUIT WITH THE NOR MEMORY AND A TERMINAL IN CIRCUIT WITH THE CAPACITOR, A FIRST NOR HAVING AN INPUT CONNECTED TO THE OUTPUT TERMINAL OF THE TIMER, A LEAD TRAIL MODULE HAVING AN OUTPUT CONNECTED TO A SECOND INPUT OF SAID FIRST NOR, SAID LEAD TRIAL MODULE BEING ARRANGED TO SUPPLY A SIGNAL CHANGE FOR SWITCHING SAID FIRST NOR AT THE END OF EACH HALF CYCLE OF ONE POLARITY OF AN ALTERNATING VOLTAGE SUPPLY, A SECOND AND A THRID NOR CONNECTED AS A NOR MEMORY WITH THE SECOND OF SAID NORS HAVING AN INPUT CONNECTED TO AN OUTPUT OF THE FIRST NOR AND THE THIRD OF NORS HAVING AN INPUT TERMINAL AND AN OUTPUT TERMINAL, A DELAYED FIRING MODULE HAVING AN OUTPUT CONNECTED TO THE INPUT OF THE THIRD NOR AND ARRANGED FOR SUPPLYING A PREDETERMINED INSTANT DURING EACH HAFL CYCLE OF AN ALTERNATING VOLTAGE SOURCE WHICH IS OPPOSITE IN POLARITY OF THE HALF CYCLE DURING WHICH THE LEAD TRIAL MODULE SUPPLIES A SIGNAL CHANGE, A PLURALITY OF ADJUSTABLE RESISTORS EQUAL IN NUMBER TO THE PERIODS OF OPERATION TO BE SEQUENTIALLY TIMED BY THE RESISTANCE WELDER CONTROL, A COUNTER HAVING AN INPUT TERMINAL CONNECTED TO THE OUTPUT TERMINAL OF THE THIRD NOR AND HAVING A PLURALITY OF NOR UNITS AR-