Integrated circuit logic

Claim 1

A LOGIC CIRCUIT CONSTRUCTED IN INTEGRATED CIRCUIT FORM AND RESPONSIVE TO A BINARY LOGIC INPUT SIGNAL HAVING FIRST AND SECOND VOLTAGE LEVELS WITH RESPECT TO A REFERENCE POTENTIAL, SUCH LOGIC CIRCUIT INCLUDING IN COMBINATION: A FIRST TRANSISTOR AND A PLURALITY OF SECOND TRANSISTORS OF THE SAME CONDUCTIVITY TYPE EACH INCLUDING AN EMITTER, A COLLECTOR AND A BASE ELECTRODE, SAD EMITTER ELECTRODES AND SAID COLLECTOR ELECTRODES OF SAID SECOND TRANSISTORS BEING CONNECTED TOGETHER RESPECTIVELY; MEANS FOR CONNECTION TO A POWER SUPPLY AND INCLUDING A FIRST CONDUCTOR AT THE REFERENCE POTENTIAL AND A SECOND CONDUCTOR PROVIDING A DIRECT CURRENT POTENTIAL WITH RESPECT TO SID REFERENCE POTENTIAL; FIRST RESISTANCE MEANS CONNECTED BETWEEN SAID COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR AND SAID SECOND CONDUCTOR AND FORMING THE SOLE POTENTIAL SUPPLY TO SAID COLLECTOR ELECTRODE, SECOND RESISTANCE MEANS CONNECTED BETWEEN SAID COLLECTOR ELECTRODES OF SAID SECOND TRANSISTORS AND SAID SECOND CONDUCTOR AND FORMING THE SOLE POTENTIAL SUPPLY TO SAID COLLECTOR ELECTRODES, AND THIRD RESISTANCE MEANS CONNECTED BETWEEN SAID FIRST CONDUCTOR AND SAID EMITTER ELECTRODES OF SAID FIRST AND SECOND TRANSISTOR; BIAS CIRCUIT MEANS COUPLED TO SAID BASE ELECTRODE OF SAID FIRST TRANSISTOR FOR ESTABLISHING THEREAT A PREDETERMINED BIAS POTENTIAL HAVING A VOLTAGE WITH RESPECT TO SAID REFERENCE POTENTIAL INTERMEDIATE SAID FIRST AND SECOND VOLTAGE LEVELS; INPUT CIRCUIT MEANS INCLUDING AN INPUT PORTION COUPLED TO SAID BASE ELECTRODE OF EACH OF SAID SECOND TRANSISTORS FOR APPLYING THERETO BINARY LOGIC INPUT SIGNALS TO SWITCH THE CIRCUIT BETWEEN A FRST STATE IN WHICH SAID FIRST TRANSISTOR IS CONDUCTIVE AND A SECOND STATE IN WHICH ONE OF SAID SECOND TRANSISTORS IS CONDUCTIVE, SAID LEVELS OF SAID INPUT SIGNALS AND SAID BIAS POTENTIAL HAVING VALUES SUCH THAT SAID FIRST AND SECOND TRANSISORS WHEN CONDUCTIVE ARE IN A NON-SATURATED CONDITION; AND OUTPUT CIRCUIT MEANS INCLUDING THIRD AND FOURTH TRANSISTORS OF THE SAME CONDUCTIVITY TYPE AS SAID FIRST AND SECOND TRANSISTORS, EACH OF SAID THIRD AND FOURTH TRANSISTORS BEING CONNECTED IN AN EMITTER FOLLOWER CIRCUIT AND HAVING A COLLECTOR ELECTRODE CONNECTED TO SAID SECOND CONDUCTOR, A BASE ELECTRODE AND AN EMITTER ELECTRODE, SAID BASE ELECTRODE OF SAID THIRD TRANSISTOR BEING CONDUCTIVELY CONNECTED TO SAID COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR AND SAID BASE ELECTRODE OF SAID FOURTH TRANSISTOR BEING CONDUCTIVELY CONNECTED TO SAID COLLECTOR ELECTRODES OF ALL SAID SECOND TRANSISTORS, AND FOURTH AND FIFTH RESISTANCE MEANS CONNECTED RESPECTIVELY BETWEEN SAID EMITTER ELECTRODES OF SAID THIRD AND FOURTH TRANSISTORS AND SAID FIRST CONDUCTOR; AND FIRST AND SECOND OUTPUT TERMINALS CONNECTED RESPECTIVELY TO SAID EMITTER ELECTRODES OF SAID THIRD AND FOURTH TRANSISTORS FOR PROVIDING BINARY LOGIC OUTPUT SIGNALS, THE BASE TO EMITTER JUNCTIONS OF SID THIRD AND FOURTH TRANSISTORS EACH TRANSLATING THE VOLTAGE LEVELS OF THE SIGNAL AT THE BASE ELECTRODE SO THAT SAID BINARY OUTPUT SIGNALS HAVE VOLTAGE LEVELS SUBSTANTIALLY THE SAME AS THE LEVELS OF THE BINARY INPUT SIGNAL.