Control apparatus

Claim 1

APPARATUS OF THE CLASS DESCRIBED COMPRISING: A BINARY COUNTER HAVING A PLURALITY OF OUTPUTS REPRESENTATIVE OF BITS OF A BINARY MEMBER; DECODER MEANS CONNECTED TO SAID BINARY COUNTER FOR DECODING THE LOWER ORDER BITS OF SAID BINARY COUNTER INTO AN EQUIVALENT NUMBER IN A SERIES OF NUMBERS HAVING A RADIX OTHER THAN TWO, AND FOR DECODING THE HIGHR ORDER OUTPUT BITS OF SAID BINARY COUNTER INTO AN EQUIVALENT NUMBER IN A SECOND SERIES OF NUMBERS HAVING A RADIX OTHER THAN TWO; MEANS FOR COMBINING THE NUMBERS OF SAID FIRST SERIES WITH THE NUMBERS OF SAID SECOND SERIES TO FORM A PLURALITY OF SIGNAL PAIRS, ONE SIGNAL IN EACH PAIR COMING FROM THE FIRST AND SECOND SERIES, THE NUMBER OF SAID PLURALITY OF SAID SIGNAL PAIRS BEING EQUAL TO THE MAXIMUM COUNT OF SAID BINARY COUNTER; A PLURALITY OF DATA GATING CIRCUITS EACH HAVING INPUTS ADAPTED TO RECEIVE INPUTS FROM SEPARATE INPUT SOURCES, AND EACH HAVING OUTPUTS ADAPTED TO BE CONNECTED TO A LOAD; MEANS CONNECTING SAID PLURALITY OF SIGNAL PAIRS OF SAID PLURALITY OF DATA GATING CIRCUITS WHEREBY EACH SIGNAL PAIR OF SAID PLURALITY CONTROLS THE CONDUCTION OF ONE OF SAID PLURALITY OF DATA GATING CIRCUITS;