Buffer with delay line recirculation

Claim 1

AN ELECTRICAL BUFFER CIRCUIT IONCLUDING: RECICULATING DELAY MEANS FOR CARRYING BITS OF BINARY DATA IN A SERIES OF SUCCESSIVE BIT POSITIONS, SAID BINARY DATA INCLUDING A MULTI-BIT BINARY INFORMATION WORD AND FIRST AND SECOND MULTI-BIT BINARY CONTROL WORDS CARRIED IN SAID DELAY MEANS IN A BIT-INTERLACED RELATIONSHIP WITH ONE ANOTHER; CIRCULATING CIRCUITRY COUPLED TO SAID DEALY MEANS FOR CAUSING THE INTERLACED BINARY WORDS TO BE CIRCULATED THROUGH SAID DELAY MEANS AT SUCCESSIVE BIT TIMES; FIRST LOGIC CIRCUITY COUPLED TO SAID DELAY MEANS FOR CAUSING SAID FIRST MULTI-BIT CONTROL WORD TO HAVE A PREDETERMINED PATTERN OF UNIT AND ZERO BINARY BITS; SECOND LOGIC CIRCUITRY COUPLED TO SAID DELAY MEANS FOR CAUSING SAID SECOND MULTI-BIT CONTROL WORD TO HAVE A PREDETERMINED PATTERN OF UNIT AND ZERO BINARY BITS; NETWORK MEANS INCLUDED IN SAID CIRCULATING CIRCUITRY FOR CAUSING THE TIMING OF SAID FIRST CONTROL WORD TO CHANGE RELATIVE TO SAID SECOND CONTROL WORD FOR EACH CIRCULATION THEREOF THROUGH SAID DELAY MEANS; AND CIRCUIT MEANS COUPLED TO SAID DELAY MEANS FOR PASSING SUCCESSIVE BITS OF SAID INFORMATION WORD ION RESPONSE TO THE CONTROL EXERTED BY SAID FIRST AND SECOND CONTROL WORDS.