Matrix logic computer

Claim 1

A SHIFT REGISTER NETWORK COMPRISING N FLIP-FLOPS EACH OF SAID FLIP-FLOPS HAVING A PAIR OF COMPLEMENTARY OUTPUTS AND A PAIR OF COMPLEMENTARY INPUTS, SAID FLIPFLOPS BEING ORDERED TO REPRESENT 20, 21, 22, . . . 2N-1, ONE OF SAID OUTPUTS AND ONE OF SAID INPUTS OF EACH FLIP-FLOP BEING DESIGNATED AS BINARY ZERO, THE OTHER OF SAID OUTPUTS AND THE OTHER OF SAID INPUTS OF EACH FLIP-FLOP BEING DESIGNATED AS A BINARY ONE, A SWITCH MATRIX HAVING 4N COLUMNS AND 2N ROWS, THE FIRST 2N OF SAID COLUMNS BEING CONNECTED TO BE RESPONSIVE TO SIGNALS DERIVING FROM SAID OUTPUTS AND THE OTHER 2N OF SAID COLUMNS BEING CONNECTED TO COUPLE SIGNALS TO SAID INPUTS, SAID ROWS BEING DESIGNATED AS BINARY ZEROS AND ONES OF THE RESPECTIVE FLIPFLOP ORDERS, SAID SWITCH MATRIX INCLUDING: FIRST AND GATE MEANS CONNECTED ONLY BETWEEN THE COLUMN CONNECTED TO THE BINARY ZERO OUTPUT OF THE KTH ORDER FLIP-FLOP AND THE FOW DESIGNATED AS THE BINARY ZERO OF THE KTH ORDER FLIP-FLOP, WHERE K IS EVERY INTEGER LESS THAN N, SECOND AND GATE MEANS CONNECTED ONLY BETWEEN THE COLUMN CONNECTED, THE BINARY ONE OUTPUT OF THE ITH ORDER FLIPFLOP AND THE ROW DESIGNATED AS THE BINARY ONE OF THE ITH ORDER FLIP-FLOP, WHER I IS EVERY INTEGER LESS THAN H, FIRST OR GATE MEANS CONNECTED ONLY BETWEEN THE COLUMN CONNECTED TO THE BINARY ONE INPUT OF THE (L+1) THE ORDER FLIPFLOP AND THE ROW DESIGNATED AS THE BINARY ONE OF THE LTH FLIP-FLOP, WHERE L IS EVERY INTEGER LESS THAN N, AND SECOND OR GATE MEANS CONNECTED ONLY BETWEEN THE COLUMN CONNECTED TO THE BINARY ONE INPUT OF THE (G+1)TH ORDER FLIPFLOP AND THE ROW DESIGNATED AS THE BINARY ONE OF THE GTH FLIP-FLOP, WHERE G IS EVERY INTEGER LESS THAN N AND THE NTH ORDER FLIP-FLOP IS THE ZERO ORDER FLIP-FLOP.