Parallel input extreme signal indicator having a control impedance in a common current path

Claim 1

AN APPARATUS FOR PROVIDING AN INDICATION OF THE IDENTITY OF THE EXTREME SIGNAL OF A PLURALITY OF N INPUT SIGNALS COMPRISING, IN COMBINATION: A PLURALITY OF TRANSISTORS; A PLURALITY OF N CURRENT PATHS, EACH INCLUDING THE EMITTERBASE CURRENT PATH OF ONE OF SAID PLURALITY OF N TRANSISTORS; ANOTHER CURRENT PATH, INCLUDING A VOLTAGE SOURCE AND AN IMPEDANCE, CONNECTED TO ALL OF SAID PLURALITY OF N CURRENT PATHS CAUSING THE CURRENT IN ALL OF SAID PLURALITY OF N CURRENT PATHS TO FLOW THROUGH SAID IMPEDANCE GENERATING A BACK-BIASING SIGNAL TO CAUSE THE ASYMMETRICALLY-CONDUCTING IMPEDANCES CORRESPONDING TO ALL INPUT SIGNALS EXCEPT THE MOST EXTREME INPUT SIGNAL TO HINDER THE FLOW OF CURRENT IN THEIR RESPECTIVE PATHS; A PLURALITY OF N SWITCHING DEVICES, EACH CONTROLLED BY THE COLLECTOR CURRENT OF ONE OF SAID PLURALITY OF N TRANSISTORS; A REJECT SWITCHING DEVICE CONTOLLED BY SAID PLURALITY OF N SWITCHING DEVICES SUCH THAT THE REJECT SWITCHING DEVICE IS OPERATED WHEN MORE THAN ONE OF SAID PLURALITY OF N SWITCHING DEVICES IS OPERATED; AND MEANS FOR APPLYING EACH OF SAID PLURALITY OF N INPUTS SIGNALS TO A CORRESPONDING ONE OF SAID PLURALITY OF N CURRENT PATHS; WHEREBY THE SWITCHING DEVICE CORRESPONDING TO THE EXTREME SIGNAL OF SAID PLURALITY OF N INPUT SIGNALS IS OPERATED.

Claim 2

AN APPARATUS FOR PROVIDING AN INDICATION OF THE IDENTITY OF THE EXTREME SIGNAL OF A PLURALITY OF N INPUT SIGNALS COMPRISING, IN COMBINATION: A PLURALITY OF TRANSISTORS; A PLURALITY OF N CURRENT PATHS, EACH INCLUDING THE EMITTERBASE CURRENT PATH OF ONE OF SAID PLURALITY OF N TRANSISTORS; ANOTHER CURRENT PATH, INCLUDING A VOLTAGE SOURCE AND AN IMPEDANCE, CONNECTED TO ALL OF SAID PLURALITY OF N CURRENT PATHS CAUSING THE CURRENT IN ALL OF SAID PLURALITY OF N CURRENT PATHS TO FLOW THROUGH SAID IMPEDANCE GENERATING A BACK-BIASING SIGNAL TO CAUSE THE ASYMMETRICALLY-CONDUCTING IMPEDANCES CORRESPONDING TO ALL INPUT SIGNALS EXCEPT THE MOST EXTREME INPUT SIGNAL TO HINDER THE FLOW OF CURRENT IN THEIR RESPECTIVE PATHS; A PLURALITY OF N SWITCHING DEVICES, EACH CONTROLLED BY THE COLLECTOR CURRENT OF ONE OF SAID PLURALITY OF N TRANSISTORS; A REJECT SWITCHING DEVICE CONTOLLED BY SAID PLURALITY OF N SWITCHING DEVICES SUCH THAT THE REJECT SWITCHING DEVICE IS OPERATED WHEN MORE THAN ONE OF SAID PLURALITY OF N SWITCHING DEVICES IS OPERATED; AND MEANS FOR APPLYING EACH OF SAID PLURALITY OF N INPUTS SIGNALS TO A CORRESPONDING ONE OF SAID PLURALITY OF N CURRENT PATHS; WHEREBY THE SWITCHING DEVICE CORRESPONDING TO THE EXTREME SIGNAL OF SAID PLURALITY OF N INPUT SIGNALS IS OPERATED.