US3215987A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic data processing
Assignee: GTE Sylvania Inc
•
Filing: 1962-06-04
•
Granted: 1965-11-02
•
Expires: 1982-06-04
Abstract
No abstract record available.
Inventors
- 👤 Terzian John
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:50
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F3/00; G06F3/01; G06F3/02; G06F3/0227; G06F9/00; G06F9/06; G06F9/22; G06F9/226
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
342 words
FOR THE PROCESSING OF DATA IN THE FORM OF DISCRETE ELECTRICAL SIGNALS CORRESPONDING TO THE COMPONENT BITS OF A DATA WORD THE COMBINATION OF: A FIRST DATA TRANSFER BUS HAVING A PLURALITY OF INDIVIDUAL CONDUCTORS CORRESPONDING TO THE INDIVIDUAL BITS OF SAID DATA WORD; A SECOND DATA TRANSFER BUS HAVING A PLURALITY OF INDIVIDUAL CONDUCTORS CORRESPONDING TO THE INDIVIDUAL BITS OF SAID DATA WORD; A DATA WORD STORAGE SUBSYSTEM HAVING AT LEAST ONE DATA BUFFER REGISTER COMPRISING A PLURALITY OF INDIVIDUAL SIGNAL STAGES WHICH CORRESPOND TO THE INDIVIDUAL COMPONENT BITS OF SAID DATA TRANSFER RELATIONSHIP TO CORRESPONDNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST BUS CONDUCTORS AND SAID SECOND BUS CONDUCTORS; MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STATES AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES; AN ARITHMETIC SUBSYSTEM HAVING AT LEAST ONE DATA PROCESSING REGISTER COMPRISING A PLURALITY OF INDIVIDUAL SIGNAL STAGES WHICH CORRESPOND TO THE INDIVIDUAL COMPONENT BITS OF SAID DATA WORD AND ARE INDIVIDUALLY CONNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST AND SECOND BUS CONDUCTORS, AND AN ARITHMETIC LOGIC UNIT COMPRISING A PLURALITY OF STAGES OF LOGIC CIRCUITS EACH CONNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST AND SECOND BUS CONDUCTORS; MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STAGES OF SID ARITHMETIC REGISTER AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES; MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STAGES OF SAID ARITHMETIC LOGIC UNIT AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES; A DATA INPUT-OUTPUT SUBSYSTEM HAVING AT LEAST ONE DATA BUFFER REGISTER COMPRISING A PLURALITY OF INDIVIDUAL SIGNAL STAGES WHICH CORRESPOND TO THE INDIVIDUAL COMPONENT BITS OF SAID DATA WORD AND ARE INDIVIDUALLY CONNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST AND SECOND BUS CONDUCTORS; AND, MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STAGES OF SAID INPUTOUTPUT REGISTER AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES.
Claim 2
Dependent Claim
342 words
FOR THE PROCESSING OF DATA IN THE FORM OF DISCRETE ELECTRICAL SIGNALS CORRESPONDING TO THE COMPONENT BITS OF A DATA WORD THE COMBINATION OF: A FIRST DATA TRANSFER BUS HAVING A PLURALITY OF INDIVIDUAL CONDUCTORS CORRESPONDING TO THE INDIVIDUAL BITS OF SAID DATA WORD; A SECOND DATA TRANSFER BUS HAVING A PLURALITY OF INDIVIDUAL CONDUCTORS CORRESPONDING TO THE INDIVIDUAL BITS OF SAID DATA WORD; A DATA WORD STORAGE SUBSYSTEM HAVING AT LEAST ONE DATA BUFFER REGISTER COMPRISING A PLURALITY OF INDIVIDUAL SIGNAL STAGES WHICH CORRESPOND TO THE INDIVIDUAL COMPONENT BITS OF SAID DATA TRANSFER RELATIONSHIP TO CORRESPONDNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST BUS CONDUCTORS AND SAID SECOND BUS CONDUCTORS; MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STATES AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES; AN ARITHMETIC SUBSYSTEM HAVING AT LEAST ONE DATA PROCESSING REGISTER COMPRISING A PLURALITY OF INDIVIDUAL SIGNAL STAGES WHICH CORRESPOND TO THE INDIVIDUAL COMPONENT BITS OF SAID DATA WORD AND ARE INDIVIDUALLY CONNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST AND SECOND BUS CONDUCTORS, AND AN ARITHMETIC LOGIC UNIT COMPRISING A PLURALITY OF STAGES OF LOGIC CIRCUITS EACH CONNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST AND SECOND BUS CONDUCTORS; MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STAGES OF SID ARITHMETIC REGISTER AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES; MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STAGES OF SAID ARITHMETIC LOGIC UNIT AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES; A DATA INPUT-OUTPUT SUBSYSTEM HAVING AT LEAST ONE DATA BUFFER REGISTER COMPRISING A PLURALITY OF INDIVIDUAL SIGNAL STAGES WHICH CORRESPOND TO THE INDIVIDUAL COMPONENT BITS OF SAID DATA WORD AND ARE INDIVIDUALLY CONNECTED IN DIRECT DATA TRANSFER RELATIONSHIP TO CORRESPONDING INDIVIDUAL ONES OF SAID FIRST AND SECOND BUS CONDUCTORS; AND, MEANS FOR PARALLEL TRANSFER OF DATA BETWEEN SAID INDIVIDUAL STAGES OF SAID INPUTOUTPUT REGISTER AND SAID CORRESPONDING INDIVIDUAL CONDUCTORS OF SAID FIRST AND SECOND BUSES.
References Cited (Backward Citations)
US2936116A
Cited
US2901166A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-11-01 | 1969-05-03 | 1969-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-11-01 | 1973-05-03 | 1973-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-11-01 | 1977-05-03 | 1977-11-02 | $7700.00 | Window Closed / Lapsed |