← Back to Patent Explorer
US3201851A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making interconnecting multilayer circuits

Assignee: Lockheed Martin Corp
•
Filing: 1960-10-05
•
Granted: 1965-08-24
•
Expires: 1980-10-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

No abstract record available.

Inventors

  • 👤 Thomas H Stearns

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 22:22
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/40; H05K3/42; H05K3/429; H05K3/0011; H05K3/0044; H05K3/0047; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0129; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0382; H05K2203/00; H05K2203/11; H05K2203/1105; H05K3/4092; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49165; Y10T29/49167

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 174 words
THE METHOD OF MAKING A PLURALITY OF CIRCUITS INTERCONNECTED AT A PLURALITY OF DISCRETE POINTS, SAID METHOD COMPRISING THE STEPS OF PLACING ON A BASE PLATE A FIRST LAYER OF THERMOPLASTIC MATERIAL HAVING A COPPER FOIL BONDED THERETO, ETCHING AN INSULATING PATH AROUND A DESIRED CIRCUIT CONFIGURATION TO PROVIDE AN INSUATED SPACE BETWEEN THE DESIRED CIRCUIT CONFIGURATION AND THE REMAINING COPPER FOIL, FORMING DIMPLED PORTIONS IN SAID CIRCUIT CONFIGURATION AT SAID DISCRETE POINTS, AND LAMINATING SUCCEEDING LAYERS OF THERMOPLASTIC MATERIAL AND COPPER FOIL THEREON, ETCHING THE FOIL AND FORMING DIMPLED PORTIONS IN A SIMILAR MANNER, SIMULTANEOUSLY APPLYING HEAT AND A CUTTING FORCE THROUGH SAID ALIGNED DIMPLED PORTIONS TO PROVIDE A HOLE THERETHROUGH AND TO MELT OUT THERMOPLASTIC MATERIAL IN THE IMMEDIATE VICINITY OF THE HOLE TO EXPOSE FOR A CONNECTION THESE DIMPLED PORTIONS HAVING HOLES THERETHROUGH, ELECTROCONDUCTIVELY SENSITIZING THE WALLS OF SAID HOLE AND EXPOSE DIMPLED CONDUCTIVE PORTIONS AND THEREAFTER ELECTROPLATING SAID WALL AND CONDUCTIVE PORTIONS WITH A CONDUCTIVE MATERIAL TO PROVIDE A MECHANICAL AND ELECTRICAL INTERCONNECTION BETWEEN SAID CIRCUITS AT SAID DISCRETE POINTS.
Claim 2
Independent Claim 174 words
THE METHOD OF MAKING A PLURALITY OF CIRCUITS INTERCONNECTED AT A PLURALITY OF DISCRETE POINTS, SAID METHOD COMPRISING THE STEPS OF PLACING ON A BASE PLATE A FIRST LAYER OF THERMOPLASTIC MATERIAL HAVING A COPPER FOIL BONDED THERETO, ETCHING AN INSULATING PATH AROUND A DESIRED CIRCUIT CONFIGURATION TO PROVIDE AN INSUATED SPACE BETWEEN THE DESIRED CIRCUIT CONFIGURATION AND THE REMAINING COPPER FOIL, FORMING DIMPLED PORTIONS IN SAID CIRCUIT CONFIGURATION AT SAID DISCRETE POINTS, AND LAMINATING SUCCEEDING LAYERS OF THERMOPLASTIC MATERIAL AND COPPER FOIL THEREON, ETCHING THE FOIL AND FORMING DIMPLED PORTIONS IN A SIMILAR MANNER, SIMULTANEOUSLY APPLYING HEAT AND A CUTTING FORCE THROUGH SAID ALIGNED DIMPLED PORTIONS TO PROVIDE A HOLE THERETHROUGH AND TO MELT OUT THERMOPLASTIC MATERIAL IN THE IMMEDIATE VICINITY OF THE HOLE TO EXPOSE FOR A CONNECTION THESE DIMPLED PORTIONS HAVING HOLES THERETHROUGH, ELECTROCONDUCTIVELY SENSITIZING THE WALLS OF SAID HOLE AND EXPOSE DIMPLED CONDUCTIVE PORTIONS AND THEREAFTER ELECTROPLATING SAID WALL AND CONDUCTIVE PORTIONS WITH A CONDUCTIVE MATERIAL TO PROVIDE A MECHANICAL AND ELECTRICAL INTERCONNECTION BETWEEN SAID CIRCUITS AT SAID DISCRETE POINTS.

References Cited (Backward Citations)

US2734150A Cited
US2502291A Cited
US2586854A Cited
US2897409A Cited
US2872391A Cited
US2889393A Cited
US2907925A Cited
US2958120A Cited
US2876393A Cited
US3037265A Cited
US2990310A Cited
US3102213A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1968-08-23 1969-02-22 1969-08-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1972-08-23 1973-02-22 1973-08-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1976-08-23 1977-02-22 1977-08-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag