Missing bit detector on recorded storage media

Claim 1

APPARATUS FOR DETECTING IRREGULARITIES IN A COLUMN OF BINARY BITS RECORDED ON A STORAGE MEDIA COMPRISING, A PLURALITY OF SENSING MEANS EACH ADAPTED TO SENSE ONE OF THE BINARY BITS OF A COLUMN OF BINARY BITS AND TO GENERATE A SENSING SIGNAL WHEN A BIT IS SENSED, A FIRST CIRCUIT CONNECTED TO SAID SENSING MEANS AND ADAPTED TO GENERATE A FIRST GATING SIGNAL IN RESPONSE TO SENSING SIGNALS RECEIVED FROM ANY OF SAID SENSING MEANS, A SECOND CIRCUIT CONNECTED TO SAID SENSING MEANS AND ADAPTED TO GENERATE A SECOND GATING SIGNAL WHEN SAID SECOND CIRCUIT RECEIVES SENSING SIGNALS FROM ALL OF SAID SENSING MEANS, A BISTABLE CIRCUIT CONNECTED TO RECEIVE SAID FIRST AND SECOND GATING SIGNALS AND ADAPTED TO ASSUME A FIRST STABLE STATE UPON RECEIPT OF SAID FIRST GATING SIGNAL AND TO ASSUME A SECOND STABLE STATE UPON RECEIPT OF SAID SECOND GATING SIGNAL, TIMING MEANS CONNECTED TO RECEIVE SAID FIRST GATING SIGNAL AND ADAPTED TO ASSUME A TIMING STATE FOR A PREDETERMINED TIME UPON RECEIPT OF SAID FIRST GATING SIGNAL, AND MEANS CONNECTED TO SAID BISTABLE CIRCUIT AND TO SAID TIMING MEANS FOR GENERATING AN ERROR SIGNAL WHEN SAID BISTABLE CIRCUIT IS IN SAID FIRST STABLE STATE WHILE SAID TIMING MEANS IS NOT IN SAID TIMING STATE.