Timing circuit

Claim 1

A TIMING CIRCUIT, INCLUDING, A PULSE SOURCE, A FIRST CAPACITOR HAVING FIRST AND SECOND TERMINALS AND HAVING ITS FIRST TERMINAL COUPLED TO SAID PULSE SOURCE FOR PROVIDING A CHARGE IN THE CAPACITOR, A FIRST TRANSISTOR HAVING A FIRST ELECTRODE COUPLED TO THE FIRST TERMINAL OF SAID CAPACITOR AND HAVING A SECONE ELECTRODE AND A THIRD ELECTRODE, SAID FIRST TRANSISTOR HAVING A NORMAL HIGH IMPEDANCE CONDITION AND AN OPERATIVELY LOW IMPEDANCE CONDITION AND BEING RESPONSIVE TO A PREDETERMINED POTENTIAL ACROSS SAID CAPACITOR FOR OPERATING TO SAID LOW IMPEDANCE CONDITION, AN OUTPUT DEVICE HAVING A FIRST TERMINAL CONNECTED TO THE SECOND ELECTRODE OF SAID FIRST TRANSISTOR TO BECOME OPERATIVE UPON A LOW IMPEDANCE IN THE FIRST TRANSISTOR, THE OUTPUT DEVICE HAVING A SECOND TERMINAL CONNECTED TO THE SECOND TERMINAL OF THE CAPACITOR, A SECOND TRANSISTOR HAVING A FIRST ELECTRODE COUPLED TO SAID THIRD ELECTRODE OF SAID FIRST TRANSISTOR AND TO SAID SOURCE, THE SECOND TRANSISTOR HAVING A SECOND ELECTRODE CONNECTED TO SAID SOURCE, AND THE SECOND TRANSISTOR HAVING A THIRD ELECTRODE CONNECTED TO THE SECONE TERMINAL OF SAID OUTPUT DEVICE, SAID SECOND TRANSSISTOR HAVING A NORMALLY NONCONDUCTIVE AND AN OPERATIVE CONDUCTIVE CONDITION, AND CONTROL MEANS INCLUDING SAID CAPACITOR AND COUPLED TO SAID SOURCE FOR MAINTAINING SAID SECOND TRANSISTOR IN ITS NONCONDUCTIVE CONDITION DURING THE TIME A PULSE IS SUPPLIED FROM SAID SOURCE AND FOR OPERATING TO SAID SECOND TRANSISTOR TO THE CONDUCTIVE CONDITION TO DISCHARGE SAID CAPACITOR AT THE END OF A PULSE FROM SAID SOURCE.