US3167757A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Converter
Assignee: RTX Corp
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Filing: 1960-10-24
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Granted: 1965-01-26
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Expires: 1980-10-24
Abstract
No abstract record available.
Inventors
- 👤 Aquila Joseph A D
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
162 words
IN AN ANALOG TO DIGITAL CONVERTER, A COMPARATOR ENERGIZED BY THE ANALOG SIGNAL TO BE CONVERTED AND BY A VARIABLE VOLTAGE LEVEL INPUT, MEANS FOR PRODUCING A FIXED LEVEL VOLTAGE CORRESPONDING TO EACH ORDER OF THE DIGITAL NUMBER TO BE FOUND AND ADDITIVELY COUPLING EACH OF SAID VOLTAGES IN TIME SEQUENCE TO SAID INPUT FROM THE HIGHEST ORDER TO THE LOWEST ORDER, MEANS INCLUDING SAID COMPARATOR FOR SEQUENTIALLY COMPARING SAID ADDITIVE VOLTAGE AT THE INPUT WITH THE ANALOG SIGNAL AFTER EACH FIXED LEVEL VOLTAGE HAS BEEN ADDED AND FOR REMOVING THE PREVIOUSLY ADDED FIXED LEVEL VOLTAGE FROM THE INPUT IN THE EVENT THAT THE VOLTAGE LEVEL AT SAID INPUT EXCEEDS THE ANALOG SIGNAL, SAID LAST MENTIONED MEANS INCLUDING TIME DELAY MEANS FOR DELAYING EACH COMPARISION OF SAID FIXED LEVEL VOLTAGES WITH SAID ANALOG VOLTAGE UNTIL A TIME PERIOD AFTER EACH FIXED LEVEL VOLTAGE IS PRODUCED, AND MEANS FOR READING OUT THE VARIOUS ORDERS OF SAID DIGITAL NUMBER CONTAINED IN SAID ANALOG SIGNAL.
Claim 2
Dependent Claim
162 words
IN AN ANALOG TO DIGITAL CONVERTER, A COMPARATOR ENERGIZED BY THE ANALOG SIGNAL TO BE CONVERTED AND BY A VARIABLE VOLTAGE LEVEL INPUT, MEANS FOR PRODUCING A FIXED LEVEL VOLTAGE CORRESPONDING TO EACH ORDER OF THE DIGITAL NUMBER TO BE FOUND AND ADDITIVELY COUPLING EACH OF SAID VOLTAGES IN TIME SEQUENCE TO SAID INPUT FROM THE HIGHEST ORDER TO THE LOWEST ORDER, MEANS INCLUDING SAID COMPARATOR FOR SEQUENTIALLY COMPARING SAID ADDITIVE VOLTAGE AT THE INPUT WITH THE ANALOG SIGNAL AFTER EACH FIXED LEVEL VOLTAGE HAS BEEN ADDED AND FOR REMOVING THE PREVIOUSLY ADDED FIXED LEVEL VOLTAGE FROM THE INPUT IN THE EVENT THAT THE VOLTAGE LEVEL AT SAID INPUT EXCEEDS THE ANALOG SIGNAL, SAID LAST MENTIONED MEANS INCLUDING TIME DELAY MEANS FOR DELAYING EACH COMPARISION OF SAID FIXED LEVEL VOLTAGES WITH SAID ANALOG VOLTAGE UNTIL A TIME PERIOD AFTER EACH FIXED LEVEL VOLTAGE IS PRODUCED, AND MEANS FOR READING OUT THE VARIOUS ORDERS OF SAID DIGITAL NUMBER CONTAINED IN SAID ANALOG SIGNAL.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-01-26 | 1968-07-27 | 1969-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-01-26 | 1972-07-27 | 1973-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-01-26 | 1976-07-27 | 1977-01-26 | $7700.00 | Window Closed / Lapsed |