Analog data encoder

Claim 1

AN ANALOG DATA ENCODER COMPRISING REVERSIBLE BINARY COUNTER MEANS, MEANS ADAPTED TO BE RESPONSIVE TO A REFERENCE WAVE SIGNAL FOR PRODUCING A SIGNAL CORRESPONDING TO THE EXISTING COUNT REPRESENTED BY SAID COUNTER MEANS, MEANS FOR COMPARING SAID SIGNAL WITH AN UNKNOWN SIGNAL TO PRODUCE AN ERROR SIGNAL, AN INTEGRATOR CIRCUIT HAVING CAPACITOR MEANS CONNECTED TO SAID COMPARING MEANS, A PULSE FORMING CIRCUIT, SWITCH MEANS INTERPOSED BETWEEN SAID INTERGRATOR CIRCUIT AND SAID PULSE FORMING CIRCUIT AND ADAPTED TO BE RESPONSIVE TO SAID REFERENCE WAVE SIGNAL FOR CLOSING SAID INTEGRATOR CIRCUIT TO RENDER SAID INTEGRATOR CIRCUIT RESPONSIVE TO SAID ERROR SIGNAL TO CHARGE SAID CAPACITOR MEANS DURING POSITIVE HALF CYCLES OF SAID REFERENCE WAVE SIGNAL AND FOR CONNECTING SAID PULSE FORMING CIRCUIT ACROSS SAID CAPACITOR MEANS TO DISCHARGE SAID CAPACITOR MEANS THERETHROUGH DURING NEGATIVE HALF CYCLES OF SAID REFERENCE WAVE SIGNAL TO PRODUCE ERROR PULSES, AND MEANS RESPONSIVE TO SAID ERROR PULSES FOR PRODUCING A SIGNAL TO ACTIVATE SAID COUNTER MEANS AND A SIGNAL TO CONTROL SAID COUNTER MEANS IN EITHER A FORWARD OR BACKWARD DIRECTION TO ADD TO OR SUBTRACT FROM SAID EXISTING COUNT DEPENDING ON THE POLARITY OF SAID ERROR PULSES UNTIL SAID ERROE SIGNAL IS ELIMINATED, WHEREBY THE COUNT IN SAID COUNTER MEANS AFTER SAID ERROR SIGNAL IS ELIMINATED REPRESENTS SAID UNKNOWN SIGNAL.