Annunciator system with acknowledgment and reset

Claim 1

IN AN ANNUCIATOR CIRCUIT FOR MONITORING A NUMBER OF VARIABLES AND INCLUDING FOR EACH VARIABLE ALARM MEANS FOR PROVIDING AN ALERT INDICATION, VARIABLE RESPONSIVE MEANS HAVING NORMAL AND ABNORMAL CONDITIONS WHEN THE ASSOCIATED VARIABLE IS RESPECTIVELY NORMAL AND ABNORMAL, AND MANUALLY OPERABLE RESET SWITCH MEANS, THE IMPROVEMENT COMPRISING A SEPARATE CONTROL CIRCUIT RESPONSIVE TO EACH VARIABLE RESPONSIVE MEANS AND SAID RESET SWITCH MEANS FOR CONTROLLING THE ASSOCIATED ALARM MEANS, EACH CONTROL CIRCUIT INCLUDING: A FIRST BISTABLE CIRCUIT HAVING A FIRST INPUT TERMINAL FOR RECEIVING A CONTROL VOLTAGE OF A GIVEN POLARITY FOR SETTING THE BISTABLE CIRCUIT AND A SECOND INPUT TERMINAL FOR RECEIVING A CONTROL VOLTAGE OF A GIVEN POLARITY WHICH RESETS THE BISTABLE CIRCUIT, MEANS RESPONSIVE TO THE SETTING AND RESETTING OF SAID BISTABLE CIRCUIT FOR RESPECTIVELY ENERGIZING AND DE-ENERGIZING SAID ALARM MEANS, A SOURCE OF SAID CONTROL VOLTAGE FOR SETTING SUCH FIRST BISTABLE CIRCUIT, MEANS CONNECTING SAID SOURCE OF CONTROL VOLTAGE CONTINUOUSLY TO SAID FIRST INPUT TERMINAL WHEN THE CONDITION RESPONSIVE MEANS IS IN ITS ABNORMAL CONDITION, AND A SERIES CIRCUIT OF A CAPACITOR AND A RESISTOR CONNECTED ACROSS A SOURCE OF DIRECT CURRENT VOLTAGE, MEANS COUPLING THE VOLTAGE DEVELOPED ACROSS SAID RESISTOR MEANS TO SAID SECOND INPUT OF SAID BISTABLE CIRCUIT AND INCLUDING RECTIFIER MEANS LIMITING THE VOLTAGE COUPLED THERETO A POLARITY WHICH WILL RESET THE BISTABLE CONTROL CIRCUIT, A COMMON PULSE BUS AND MEANS FOR CONTINUOUSLY PULSATING SAID PULSE BUS WITH A VOLTAGE OF A POLARITY WHICH WILL DISCHARGE SAID CAPACITOR IN EACH CONTROL CIRCUIT, EACH OF SAID CAPACITORS NORMALLY RECHARGING IN THE INTERVALS BETWEEN SAID PULSES AND THE CHARGE CURRENT GENERATING PULSES ACROSS SAID RESISTOR OF A POLARITY TO PASS THROUGH SAID ASSOCIATED RECTIFIER MEANS AND RESET THE ASSOCIATED FIRST BISTABLE CIRCUIT IF IT IS SET, WHEN THE CONTROL VOLTAGE APPLIED TO THE FIRST INPUT TERMINAL THEREOF IS REMOVED, EACH CONTROL CIRCUIT FURTHER INCLUDING A SECOND BISTABLE CIRCUIT HAVING INPUT TERMINAL MEANS FOR SETTING AND RESETTING THE SAME AND A RESET INHIBIT OUTPUT CONNECTED TO SAID CAPACITOR IN THE ASSOCIATED CONTROL CIRCUIT FOR KEEPING THE SAME DISCHARGED WHEN THE SECOND BISTABLE CIRCUIT IS SET AND ALLOWING THE CHARGE AND DISCHARGE THEREOF WHEN THE SECOND BISTABLE CIRCUIT IS RESET, AND A COMMON BUS CONNECTED THROUGH SAID MANUALLY OPERABLE RESET SWITCH MEANS TO A SOURCE OF RESET VOLTAGE FOR SAID SECOND BISTABLE CIRCUITS AND FEEDING SAID RESET VOLTAGE TO THE SECOND BISTABLE CIRCUITS OF SAID CONTROL CIRCUITS TO RESET THE SAME WHEN THE LATTER SWITCH MEANS IS OPERATED.