Decimal computer employing coincident

Claim 1

A SYSTEM FOR PERFORMING AN ARITHMETICAL OPERATION INVOLVING THE DECIMAL NUMBERS N1 AND N2 COMPRISING A FIRST DECIMAL REGISTER FOR STORING A SIGNAL REPRESENTING N1, A SECOND REGISTER FOR STORING A SIGNAL REPRESENTING N2, FIRST PULSE GENERATOR MEANS, FIRST AND SECOND DECIMAL COUNTERS, SAID FIRST AND SECOND COUNTERS AND SAID FIRST AND SECOND REGISTERS ALL BEING SEPARATE DEVICES, AN OUTPUT DECIMAL COUNTER, TWO OF SAID COUNTERS BEING RESPONSIVE TO SAID FIRST GENERATOR MEANS, SECOND PULSE GENERATOR MEANS RESPONSIVE TO THE SIGNAL STORED IN SAID SECOND REGISTER AND THE COUNT ACHIEVED BY SAID SECOND COUNTER FOR DERIVING A PULSE WHEN THE COUNT ACHIEVED BY SAID SECOND COUNTER REACHES N2, MEANS FOR CONTROLLING THE COUNT OF ONE OF SAID COUNTERS IN RESPONSE TO THE DERIVATION OF SAID PULSE BY SAID SECOND GENERATOR MEANS, THIRD PULSE GENERATOR MEANS RESPONSIVE TO THE COUNT STORED IN SAID FIRST REGISTER AND THE COUNT ACHIEVED BY SAID FIRST COUNTER FOR DERIVING A PULSE FOR DECOUPLING SAID TWO COUNTERS FROM SAID SOURCE AND FOR RESETTING BOTH OF SAID REGISTERS AND SAID FIRST AND SECOND COUNTERS TO ZERO WHEN THE FIRST COUNTER REACHES N1, AND MEANS FOR COUPLING THE PULSES DERIVED BY ONE OF SAID GENERATOR MEANS TO SAID OUTPUT COUNTER, SAID OUTPUT COUNTER BEING ADVANCED BY ONE PLACE EACH TIME THE GENERATOR MEANS TO WHICH IT IS RESPONSIVE DERIVES A PULSE.