Control system for a digital computer

Claim 1

IN A COMPUTER, THE COMBINATION OF MEMORY MEANS FOR STORING SIGNALS CORRESPONDING RESPECTIVELY TO A PLURALITY OF COMPUTER WORDS AND TO A PLURALITY OF COMPUTER COMMANDS, EACH OF SAID COMMANDS HAVING AN INSTRUCTION PORTION AND AN ADDRESS PORTION, EACH OF SAID WORDS HAVING A PREDETERMINED NUMBER OF BITS OF BINARY INFORMATION, AN N-BINARY BIT INSTRUCTION REGISTER HAVING 2N POSSIBLE STATES COUPLED TO SAID MEMORY MEANS FOR RECEIVING AND STORING THE SIGNALS FROM SAID MEMORY MEANS CORRESPONDING TO SELECTED ONES OF THE INSTRUCTION PORTIONS OF SAID COMMANDS, DECODING MEANS CONNECTED TO SAID INSTRUCTION REGISTER INCLUDING AN OUTPUT TERMINAL CORRESPONDING TO EACH OF THE 2N POSSIBLE STATES OF SAID N-BINARY BIT INSTRUCTION REGISTER, A COUNTER HAVING A PLURALITY OF BISTABLE STAGES, EACH OF SAID BISTABLE STAGES HAVING INPUT TERMINALS AND OUTPUT TERMINALS, MEANS INTERCONNECTING SAID BISTABLE STAGES, MEANS INCLUDING GATING CIRCUITS CONNECTING DIFFERENT ONES OF SAID OUTPUT TERMINALS OF SAID DECODING MEANS TO SELECTED ONES OF THE INPUT TERMINALS OF SAID BISTABLE STAGES TO PROVIDE A PREDETERMINED NON-BINARY SEQUENCE OF CONGURATIONS OF SAID BISTABLE STAGES FOR A PREDETERMINED NUMBER OF COMPUTER WORD TIMES FOR EACH OF SAID OUTPUTS, MEANS CONNECTED TO SAID OUTPUT TERMINALS OF SAID BISTABLE STAGES OF SAID COUNTER AND TO SAID INSTRUCTION REGISTER FOR PRODUCING AN OUTPUT CORRESPONDING TO THE COMBINED STATES OF SAID COUNTER AND OF SAID INSTRUCTION REGISTER FOR EXECUTING SPECIFIED FUNCTIONS IN SAID COMPUTER FOR EACH OF SAID CONFIGURATIONS AS DICTATED BY SAID INSTRUCTION PORTION OF SAID COMMAND, AND ADDITIONAL BISTABLE MEANS CONNECTED TO SAID COUNTER FOR ESTABLISHING A PREDETERMINED CONFIGURATION IN SAID COUNTER, AND MEANS CONNECTED TO SAID COUNTER AND TO SAID REGISTER FOR TRANSFERRING A NEW COMMAND FROM SAID MEMORY MEANS TO SAID INSTRUCTION REGISTER.