Computer synchronizing circuit

Claim 1

IN A COMPUTER SYNCHRONIZING CIRCUIT, A COINCIDENCE CIRCUIT INCLUDING A PLURALITY OF INPUT TERMINAL, AN OUTPUT TERMINAL AND A REFERENCE TERMINAL, A PLURALITY OF NONLINEAR ELEMENTS, SAID INPUT TERMINALS SEVERALLY CONNECTED TO ONE SIDE OF EACH OF SAID NON-LINEAR ELEMENTS, THE OTHER SIDE OF SAID NON-LINEAR ELEMENTS CONNECTED TO SAID OUTPUT TERMINAL, A SOURCE OF SYNCHRONIZING CLOCK PULSES CONNECTED BETWEEN SAID OUTPUT TERMINAL AND SAID REFERENCE TERMINAL, A SOURCE OF INFORMATION PULSES CONNECTED TO AID OUTEACH OF SAID INPUT TERMINALS, A CAPACITOR, A FIRST DIODE CONNECTED BETWEEN SAID OUTPUT TERMINAL AND ONE SIDE OF SAID CAPACITOR, A SECOND DIODE CONNECTED BETWEEN THE OTHER SIDE OF SAID CAPACITOR AND SAID REFERNECE TERMINAL, THE POLARITY OF SAID CAPACITOR AND SAID REFERENCE TERMINAL, CAPACITOR BY THE OUTPUT OF SAID COINCIDENCE CIRCUIT, A THIRD DIODE CONNECTED BETWEEN SAID ONE SIDE OF SAID CAPACITOR AND SAID CLOCK PULSE SOURCE, A LOAD CONNECTED TO SAID REFERENCE TERMINAL, A FOURTH DIODE CONNECTED BETWEEN SID LOAD AND SAID OTHER SIDE OF SAID CAPACITOR, THE POLARITY OF SAID THIRD AND FOURTH DIODES PERMITTING DISCHARGE OF SAID CAPACITOR THROUGH SAID LOAD.