Serial digital data processing circuit

Claim 1

IN A HIGH SPEED COMPOUND LOGIC CIRCUIT FOR PROCESSING DIGITAL SIGNAL INFORMATION SUPPLIED IN SUCCESSIVE DIGIT PERIODS, FIRST AND SECOND LOGIC CIRCUITS FOR PROCESSING DIGITAL INFORMATION AT DIGITAL INPUT REPETITION RATES OF ONE DIGIT EVERY TWO DIGIT PERIODS, A SIGNAL SOURCE SUPPLYING DIGITAL INFORMATION IN SUCCESSIVE DIGIT PERIODS, SAID DIGITAL SIGNALS BEING GROUPED IN ACCORDANCE WITH THEIR OCCURRENCE IN TWO INTERLEAVED SETS OF DIGIT PERIODS, FIRST AND SECOND INPUT CIRCUITS, A FIRST SWITCHING MEANS FOR APPLYING THE FIRST OF SAID GROUPS OF INPUT SIGNALS ONLY TO SAID FIRST INPUT CIRCUIT AND FOR APPLYING THE SECOND OF SAID GROUPS ONLY TO SAID SECOND INPUT CIRCUIT, CIRCUIT MEANS CONNECTING BOTH OF SAID INPUT CIRCUITS TO BOTH OF SAID LOGIC CIRCUITS FOR COUPLING SAID FIRST AND SECOND GROUPS OF INPUT SIGNALS TO BOTH OF SAID LOGIC CIRCUITS, SAID CIRCUIT MEANS INCLUDING DELAY CIRCUIT MEANS FOR SYNCHRONIZING THE ARRIVAL OF DIGITAL SIGNAL INFORMATION AT EACH LOGIC CIRCUIT FROM SAID TWO INPUT CIRCUITS, AND A SECOND SWITCHING MEANS SYNCHRONIZED WITH SAID FIRST SWITCHING CIRCUIT FOR CONVERTING THE OUTPUTS FROM SAID TWO LOGIC CIRCUITS INTO SERIAL DIGITAL OUTPUT SIGNALS IN SUCCESSIVE DIGIT PERIODS.