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JPS59205652A Expired / Lapsed JP ⏱️ 0.0 years remaining

Program tracing system

Assignee: Fuji Electric Co Ltd
•
Filing: 1983-05-06
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Granted: —
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Expires: 2003-05-06
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Abstract

Abstract PURPOSE:To reduce both trace memory capacity and information reading labor by tracing the address data by a branch instruction only in case the dissidence is obtained between an estimated address and an actually outputted address. CONSTITUTION:A trace memory control part 4 compares the contents on an address bus 6 with the contents of an address register 2 through a comparator 3 by the information fed from a processor 1. If no coincidence is obtained from this comparison, the part 4 reads out the contents held by the register 2 and writes them to a trace memory 5. Then the contents on the bus 6 are stored to the memory 5, and finally the address data on the bus 6 is stored to the register 2 for addition by an amount equal to the increment of a program counter. When the coincidence is obtained from said comparison, the contents of the register 2 are added by an amount equivalent to the increment of the program counter. Then the part 4 performs no tracing of the address data to be fed to the memory 5.

Inventors

  • 👤 Junichi Hiramatsu
  • 👤 平松 純一

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-23 14:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36

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