Semiconductor memory device with voltage stress test mode

Claim 2

A semiconductor memory device comprising: a DRAM circuit (10); a voltage stress test mode signal generating circuit (20) for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals (2a, 2b) used in a normal operation of said DRAM circuit (10); and a control circuit (21) for receiving the test mode signal from said voltage stress test mode signal generating circuit (20), and performing control such that upper bits, of an output signal from a refresh address counter (4) of said DRAM circuit (10), which are more significant than a specific bit are fixed at the same level, and lower bits which are less significant than the specific bit are subjected to a normal count operation.

Claim 3

A device according to claim 2, characterized in that said DRAM circuit (10) comprises: a memory cell array (1) having a plurality of dynamic memory cells (MC) arranged in the form of a matrix; word lines (WL), each connected to said memory cells (MC) in the same row of said memory cell array (1); bit lines (BL), each connected to said memory cells (MC) in the same column of said memory cell array (1); a bit line precharging circuit (12) connected to said bit lines (BL) and ON/OFF-controlled by a bit line equalizing signal to precharge said bit lines (BL) to a bit line precharging potential; external terminals (2a, 2b) to which a supply voltage (Vcc), an address signal (AINj), and various control signals (WE, RAS, CAS) are externally input; an address buffer circuit (3) for amplifying an external address signal input through some (2b) of said external terminals (2a, 2b); a refresh address counter (4) for generating a refresh address signal for a refresh operation of said memory cells (MC); an address switching circuit (5) for selecting either an output signal from said refresh address counter (4) or a row address signal output from said address buffer circuit (3); a row decoder circuit (6) having a word line selecting function for selecting an arbitrary row in accordance with an internal row address signal output from said address switching circuit (5); a word line driving circuit (8), having at least one word line driving MOS transistor connected between a word line driving voltage source (7) and said word lines (WL), for driving said word lines (WL) in accordance with an output signal from said row decoder circuit (6); and a sense amplifier circuit (SA) for detecting information read out from said memory cells (MC) to said bit lines (BL).

Claim 4

A device according to claim 3, characterized in that said DRAM circuit (10) includes spare word lines (SWL) and a spare row decoder/word line driving circuit (13) for a fail-safe operation, and said control circuit (21) further performs control to selectively drive said spare word lines (SWL) at the same duty ratio as that for normal word lines (WL) in a voltage stress test.

Claim 5

A device according to claim 4, characterized in that said control circuit (21) further performs control to limit a capacity of a driving transistor for said sense amplifier circuit (SA).

Claim 6

A device according to claim 5, characterized in that said DRAM circuit (10) includes a bit line transfer gate (TG) inserted between an input node of said sense amplifier circuit (SA) and said bit lines (BL) and ON/OFF-controlled by a control signal, and said control circuit (21) further controls said bit line transfer gate (TG) in an ON state in a voltage stress test.

Claim 7

A device according to claim 3, characterized in that said word line driving voltage source (7) is an external power supply for a semiconductor chip, and also serves as a booster circuit (120) for generating a word line driving voltage by boosting a supply voltage (Vcc), applied from the outside of said semiconductor chip, on said chip, and applying the word line driving voltage as power to said word line driving circuit (8).

Claim 8

A device according to claim 7, characterized in that said control circuit (21) further performs control to connect an output node of said booster circuit (120) to an external power supply terminal (2a) in a voltage stress test.

Claim 9

A device according to claim 3, characterized in that said DRAM circuit (10) further includes a supply voltage decreasing circuit (130) for decreasing a supply voltage (Vcc), applied from the outside of a semiconductor chip, on said chip, and applying the decreased voltage as power to a memory cell peripheral circuit, and said control circuit (21) further performs control to connect an output node of said supply voltage decreasing circuit (130) to an external power supply terminal (2a).

Claim 10

A device according to claim 3, characterized in that each of said dynamic memory cells (MC) includes a transfer gate (TG) constituted by an n-channel MOS transistor, and said driving MOS transistor for said word line driving circuit (8) is a p-channel MOS transistor.

Claim 11

A semiconductor memory device comprising: a DRAM circuit (10); a voltage stress test mode signal generating circuit (20) for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals (2a, 2b) used in a normal operation of said DRAM circuit (10); and a control circuit (21) for receiving the test mode signal from said voltage stress test mode signal generating circuit (20), and performing control such that all bits of an output signal from a refresh address counter (4) of said DRAM circuit (10) are fixed at the same level so as to cause a word line driving circuit (8) of said DRAM circuit (10) to simultaneously drive all word lines (WL).

Claim 12

A device according to claim 11, characterized in that said DRAM circuit (10) comprises: a memory cell array (1) having a plurality of dynamic memory cells (MC) arranged in the form of a matrix; word lines (WL), each connected to said memory cells (MC) in the same row of said memory cell array (1); bit lines (BL), each connected to said memory cells (MC) in the same column of said memory cell array (1); a bit line precharging circuit (12) connected to said bit lines (BL) and ON/OFF-controlled by a bit line equalizing signal to precharge said bit lines (BL) to a bit line precharging potential; external terminals (2a, 2b) to which a supply voltage (Vcc), an address signal (AINj), and various control signals (WE, RAS, LAS) are externally input; an address buffer circuit (3) for amplifying an external address signal input through some (2b) of said external terminals (2a, 2b); a refresh address counter (4) for generating a refresh address signal for a refresh operation of said memory cells (MC); an address switching circuit (5) for selecting either an output signal from said refresh address counter (4) or a row address signal output from said address buffer circuit (3); a row decoder circuit (6) having a word line selecting function for selecting an arbitrary row in accordance with an internal row address signal output from said address switching circuit (5); a word line driving circuit (8), having at least one word line driving MOS transistor connected between a word line driving voltage source (7) and said word lines (WL), for driving said word lines (WL) in accordance with an output signal from said row decoder circuit (6); a sense amplifier circuit (SA) for detecting information read out from said memory cells (MC) to said bit lines (BL); and a bit line transfer gate (TG) inserted between an input node of said sense amplifier circuit (SA) and said bit lines (BL) and ON/OFF-controlled by a control signal.

Claim 13

A device according to claim 12, characterized in that said DRAM circuit (10) includes spare word lines (SWL) and a spare row decoder/word line driving circuit (13) for a fail-safe operation, and said control circuit (21) further performs control to selectively drive said spare word lines (SWL) in a voltage stress test.

Claim 14

A device according to claim 13, characterized in that said control circuit (21) further performs control in a voltage stress test such that said bit line transfer gate (TG) and said bit line equalizing circuit (11) are set in an ON state, and the bit line precharging potential is set at a low level so as to inhibit operations of said sense amplifier circuit (SA) and a circuit on an output side thereof.

Claim 15

A device according to claim 12, characterized in that said word line driving voltage source (7) is an external power supply for a semiconductor chip, and also serves as a booster circuit (120) for generating a word line driving voltage by boosting a supply voltage (Vcc), applied from the outside of said semiconductor chip, on said chip, and applying the word line driving voltage as power to said word line driving circuit (8).

Claim 16

A device according to claim 15, characterized in that said control circuit (21) further performs control to connect an output node of said booster circuit (120) to an external power supply terminal (2a) in a voltage stress test.

Claim 17

A device according to claim 12, characterized in that said DRAM circuit (10) further includes a supply voltage decreasing circuit (130) for decreasing a supply voltage (Vcc), applied from the outside of a semiconductor chip, on said chip, and applying the decreased voltage as power to a memory cell peripheral circuit, and said control circuit (21) further performs control to connect an output node of said supply voltage decreasing circuit (130) to an external power supply terminal (2a).

Claim 18

A device according to claim 12, characterized in that each of said dynamic memory cells (MC) includes a transfer gate (TG) constituted by an n-channel MOS transistor, and said driving MOS transistor for said word line driving circuit (8) is a p-channel MOS transistor.