Automatic test equipment system using pin slice architecture

Claim 2

A tester for a multiple pin integrated circuit comprising: a plurality of pin slice means, each associated with a separate pin, for providing a sequence of test signals to said pin, including a memory for storing said sequence, said memory being programmable with said sequence independently from other memories for other pins; and means for programming in parallel a plurality of said pin slice means; wherein each of said pin slice means includes a plurality of parts, said means for programming in parallel including means for programming a first part of a first group of said pin slice means independently of a second part of a second, different overlapping group of said pin slice means.

Claim 3

The tester of claim 2 further comprising first and second participate memories for each of said pin slice means, said first participate memory having an output coupled to enable or disable said first part and said second participate memory have an output coupled to enable or disable said second part.

Claim 4

A tester for multiple pin integrated circuits, comprising: (a) a plurality of pin slice circuits, each coupled to a separate pin connector, each pin slice circuit including, (1) a local memory having a single bit I/O and a plurality of addresses, for storing a string of data to be applied to said pin connector, (2) sequencing means, coupled to an output of said local memory, for providing timing control of said data and including a sequencer memory for storing a plurality of timing criteria, (3) pin electronics means, coupled to an output of said sequencing means, for providing appropriate voltage and current levels to said pin connector for said data and including a voltage memory for storing voltage and current levels; and (b) a participate memory for storing at least one combination of said pin slice circuits to be programmed with identical data having outputs coupled to enabling inputs of said pin slice circuits; such that separate patterns can be written into said local memories, sequencer memories and voltage memories for independent groupings of said pin slice circuits.

Claim 5

The tester of claim 4 wherein each said pin slice circuit further includes a scrambler memory having data outputs coupled to address inputs of said sequencer memory, said scrambler memory being programmable so that a single address provided to the scrambler memory for all pin slice circuits can select different addresses in said sequencer memories for different pin slice circuits.

Claim 6

The tester of claim 4 wherein each said pin slice circuit further includes means for buffering a data stream coupled to an output of said local memory.

Claim 7

The tester of claim 4 wherein each said pin slice circuit further includes a comparator, coupled to said pin connector, for evaluating an output of said integrated circuit; a comparison memory, coupled to said comparator for storing a pass or fail indication for a plurality of tests; and a cumulative fail memory location, coupled to said comparison memory, for storing a fail signal if any location in said comparison memory has a fail signal written to it; such that said comparison memory will contain all pass signals, and thus need not be read, unless said cumulative fail memory location contains a fail signal.

Claim 8

The tester of claim 4 wherein each of said pin slice circuits further comprises a first participate memory having an output coupled to an input of said local memory, and a second participate memory having an output coupled to an input of said voltage memory.

Claim 9

The tester of claim 6 wherein said means for buffering a data stream comprises a first-in, first-out register.

Claim 10

A tester for multiple pin integrated circuits, comprising: a plurality of pin slice circuits, each coupled to a separate pin connector, each pin slice circuit including, (1) a local memory having a single bit I/O and a plurality of addresses, for storing a string of data to be applied to said pin connector, (2) sequencing means, coupled to an output of said local memory, for providing timing control of said data and including a sequencer memory for storing a plurality of timing criteria, (3) pin electronics means, coupled to an output of said sequencing means, for providing appropriate voltage and current levels to said connector for said data and including a voltage memory for storing voltage and current levels, (4) a first participate memory for storing data at addresses which indicate if said local memory is to be used for a grouping of pin slice circuits indicated by said addresses having an output coupled to an enabling input of said local memory, (5) a second participate memory for storing data at addresses which indicate if said voltage memory is to be used for a grouping of pin slice circuits indicated by said addresses having an output coupled to an enabling input of said voltage memory, and (6) a scrambler memory having data outputs coupled to address inputs of said sequencer memory, said scrambler memory being programmable so that a signal address provided to the scrambler memory for all pin slice circuits can select different addresses in said sequencer memories for different pin slice circuits; such that separate patterns can be written into said local memories, sequencer memories and voltage memories for independent groupings of said pin slice circuits.

Claim 11

The tester of claim 10 wherein each said pin slice circuit further includes a first-in, first-out register coupled to an output of said local memory.

Claim 12

The tester of claim 10 wherein each said pin slice circuit further includes a comparator, coupled to said pin connector, for evaluating an output of said integrated circuit; a comparison memory, coupled to said comparator for storing a pass or fail indication for a plurality of tests; and a cumulative fail memory location, coupled to said comparison memory, for storing a fail signal if any location in said comparison memory has a fail signal written to it; such that said comparison memory will contain all pass signals, and thus need not be read, unless said cumulative fail memory location contains a fail signal.