EP0292136A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same
Assignee: HP Inc
•
Filing: 1988-04-29
•
Granted: —
•
Expires: 2008-04-29
Abstract
Abstract Disclosed herein is a method and circuit useful in the testing of integrated circuit chips (10). On-chip test circuitry (12) is provided at a selected location on an IC chip (10) and energized while the chips (10) are still mounted on a lead frame member (48), wound on reels (68) and heated in an oven (70). Advantageously, the continuous lead frame member (62) may be a tape automated bond (TAB bond) flexible circuit (48) which is adapted for gang bonding to a large plurality of ICs before being wound on reels (68). In a preferred test circuit embodiment, the conductive on-off state of digital address circuitry (12) is controlled by applying a test signal potential to an input test pad (18) and through a fuse (20) to a common test circuit junction (21). This junction (21) is in turn connected between a transistor (38) and diode (36) in a series control network which is operative to control the conductive state cf the address circuitry (12). This network enables the input test pad (18) to be used as both a test input connection and a ground connection for the IC test circuit(12).
Inventors
- 👤 Robert W. Shreeve
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 08:14
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2868; G01R31/26; G01R31/2642; G01R31/30; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
79 words
A process for burning in an integrated circuit which includes: a. mounting a plurality of integrated circuit chips (10) on a continuous lead frame (62), b. heating said chips (10) to a predetermined elevated temperature, and c. cycling said chips (10) with test vector signals (14,16) generated from on-chip circuitry (12) for a predetermined time and at said elevated temperature to accomplish burn-in thereof without the requirement for individually mounting said chips (10) on burn-in carriers or the like.
Claim 2
Dependent Claim
79 words
A process for burning in an integrated circuit which includes: a. mounting a plurality of integrated circuit chips (10) on a continuous lead frame (62), b. heating said chips (10) to a predetermined elevated temperature, and c. cycling said chips (10) with test vector signals (14,16) generated from on-chip circuitry (12) for a predetermined time and at said elevated temperature to accomplish burn-in thereof without the requirement for individually mounting said chips (10) on burn-in carriers or the like.
Claim 3
Dependent Claim
118 words
A process for testing integrated circuit chips (10) which includes: a. providing a test signal drive (14,16) on a plurality of integrated circuit chips (10), b. securing said chips (10) to a continuous lead frame member (62), c. heating said chips (10) to a predetermined elevated temperature, d. applying an energizing voltage to said lead frame (62) to in turn energize on-chip test circuitry (12), and e. cycling said chips (10) with a test signal drive (14,16) for a predetermined time at said elevated temperature, whereby said lead frame (62) and chips (10) mounted thereon may be cooled and readied for further processing without the requirement for severing the lead frame (62) or for removing chips (10) therefrom.
Claim 4
Dependent Claim
118 words
A process for testing integrated circuit chips (10) which includes: a. providing a test signal drive (14,16) on a plurality of integrated circuit chips (10), b. securing said chips (10) to a continuous lead frame member (62), c. heating said chips (10) to a predetermined elevated temperature, d. applying an energizing voltage to said lead frame (62) to in turn energize on-chip test circuitry (12), and e. cycling said chips (10) with a test signal drive (14,16) for a predetermined time at said elevated temperature, whereby said lead frame (62) and chips (10) mounted thereon may be cooled and readied for further processing without the requirement for severing the lead frame (62) or for removing chips (10) therefrom.
Claim 5
Dependent Claim
63 words
A process for testing integrated circuits (10) which comprises: a. bonding said integrated circuits (10) to a continuous flexible lead frame member (62), b. winding said lead frame member (62) onto a reel (68), c. heating said integrated circuits (10) at a predetermined temperature for a predetermined time, and d. applying a test signal (14,16) to said integrated circuits (10) while being heated.
Claim 6
Dependent Claim
63 words
A process for testing integrated circuits (10) which comprises: a. bonding said integrated circuits (10) to a continuous flexible lead frame member (62), b. winding said lead frame member (62) onto a reel (68), c. heating said integrated circuits (10) at a predetermined temperature for a predetermined time, and d. applying a test signal (14,16) to said integrated circuits (10) while being heated.
Claim 7
Dependent Claim
51 words
The process defined in claim 3 wherein the application of a test signal includes: a. providing an on-chip test circuit segment (12) on each integrated circuit (10), and b. energizing said on-chip test circuit (12) by applying a DC bias voltage thereto and via said lead frame (62) while being heated.
Claim 8
Dependent Claim
53 words
A process for testing integrated circuit chips (10) mounted on a continuous flexible lead frame (62) which includes: a. providing on-chip test circuitry (12) within integrated circuit chips (10), and b. energizing and cycling said on-chip test circuitry (12) by applying a DC operating voltage thereto by way of said lead frame (62).
Claim 9
Dependent Claim
53 words
A process for testing integrated circuit chips (10) mounted on a continuous flexible lead frame (62) which includes: a. providing on-chip test circuitry (12) within integrated circuit chips (10), and b. energizing and cycling said on-chip test circuitry (12) by applying a DC operating voltage thereto by way of said lead frame (62).
Claim 10
Dependent Claim
43 words
The process defined in claim 5 which further includes: a. winding said lead frame (62) on a reel (68), and b. inserting said reel (68) in an oven (70) and heating said reel (68) to a predetermined elevated temperature for a predetermined time.
Claim 11
Dependent Claim
44 words
The process defined in claim 6 which further includes pre burn-in testing and post burn-in testing of said chips by moving said lead frame (62) from a supply reel (58) and through a test station area (64) and then to a take-up reel (68).
Claim 12
Dependent Claim
119 words
A test circuit (Fig. 3) for use in cycling integrated circuits (10) during burn-in, comprising: a. a test node (18) for receiving a reference potential during a test operation, b. test vector address circuity (12) for applying test vector signals to an integrated circuit during the test mode of operation, c. enable means (22) connected between said test node (18) and a segment of said address circuitry for applying an enable reference potential to said address circuitry during test operation, and d. disable means (36,38) connected between a DC dias (34) and a reference potential Vdd for switching from said test operation upon removal of said reference potential from said test node (18) and thereby disabling said address circuitry.
Claim 13
Dependent Claim
119 words
A test circuit (Fig. 3) for use in cycling integrated circuits (10) during burn-in, comprising: a. a test node (18) for receiving a reference potential during a test operation, b. test vector address circuity (12) for applying test vector signals to an integrated circuit during the test mode of operation, c. enable means (22) connected between said test node (18) and a segment of said address circuitry for applying an enable reference potential to said address circuitry during test operation, and d. disable means (36,38) connected between a DC dias (34) and a reference potential Vdd for switching from said test operation upon removal of said reference potential from said test node (18) and thereby disabling said address circuitry.
Claim 14
Dependent Claim
81 words
The test circuit defined in claim 8 wherein said disable means includes a diode (36) and a transistor (38) connected in series between a DC bias voltage Vdd and a point of reference potential (34), and both said diode (36) and transistor (38) connected to said test node (18), whereby the removal of a reference potential from said test node (18) controls conductivity in both said diode and transistor and in turn is operative to enable and disable said address circuitry.
Claim 15
Dependent Claim
23 words
The test circuit defined in claim 8 wherein said address circuitry includes an oscillator (26) connected in series with an output counter (28).
Claim 16
Dependent Claim
23 words
The test circuit defined in claim 9 wherein said address circuitry includes an oscillator (26) connected in series with an output counter (28).
Claim 17
Dependent Claim
120 words
The test circuit defined in claim 8 wherein: a. said test node (18) is connected to a common circuit junction (21) at which the voltage is switched from a high state to a low state and vice versa for controlling the conductive state of said address circuitry, b. a transistor (38) is connected between said common circuit junction (21) and a bias potential Vdd, and c. a diode (36) is connected between said common circuit junction (21) and a point of reference potential (34), whereby said diode (36) and transistor (38) alternately conduct to in turn switch said address circuitry (12) from a conductive state to a nonconductive state in the test mode and normal IC mode of operation, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.