EP0136834A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A digital circuit performing an arithmetic operation with an overflow
Assignee: NEC Corp
•
Filing: 1984-09-03
•
Granted: —
•
Expires: 2004-09-03
Abstract
Abstract Input data from a source (11) such as a multiplier is added or subtracted by an arithmetic unit (12), the result being placed in a result register (13) whose contents form one input to the arithmetic unit. A multiplexer (16) selects as the other input either the data from the source (11) or the contents of the result register and a shifter (15) is interposed between the multiplexer and the arithmetic unit. When the arithmetic unit (12) signals an overflow to a control circuit (17) the multiplexer (16) selects the result register (13) whose contents are shifted one bit by the shifter (15). A shift control register (14) is incremented. Input data from the source (11) is initially not shifted but, after one or more overflows have occurred, such data is shifted by the number of bits corresponding to the number of times that the shift control register (14) has been incremented. This arrangement simplifies both the hardware and the software cycles necessary to handle overflow.
Inventors
- 👤 Kohji C/O Nec Corporation Doi
- 👤 Yuichi C/O Nec Corporation Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 19:25
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/5443; G06F7/499; G06F7/49905; G06F7/4991
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
123 words
A digital circuit including an arithmetic unit (12) for executing addition or subtraction, a result register (13) for receiving a result from the arithmetic unit, a multiplexer (16) controlled by a control circuit (17) for selecting data to be appliex to one input of the arithmetic unit, and a shifter (15) for shifting data when an overflow condition exists, characterised in that the shifter (15) is between the multiplexer (16) and the said one input of the arithmetic unit (12), in that the multiplexer selects between input data from a source (11) thereof and the contents of the result register (13), and by a shift contro1 register (14) whose contents determine what shift if any is to be effected by the shifter (15).
Claim 2
Dependent Claim
123 words
A digital circuit including an arithmetic unit (12) for executing addition or subtraction, a result register (13) for receiving a result from the arithmetic unit, a multiplexer (16) controlled by a control circuit (17) for selecting data to be appliex to one input of the arithmetic unit, and a shifter (15) for shifting data when an overflow condition exists, characterised in that the shifter (15) is between the multiplexer (16) and the said one input of the arithmetic unit (12), in that the multiplexer selects between input data from a source (11) thereof and the contents of the result register (13), and by a shift contro1 register (14) whose contents determine what shift if any is to be effected by the shifter (15).
Claim 3
Dependent Claim
73 words
A digital circuit according to claim 1, characterised in that the control circuit (17) provides a control signal whenever an overflow occurs, in that the control signal causes the shifter (15) to shift the data from the result register (13) by one bit and also increments the control register (14), and in that the shift (15) is controlled by the contents of the control register (14) in the absence of the control signal.
Claim 4
Dependent Claim
32 words
A digital circuit according to claim 2, characterised in that the multiplexer (16) selects the contents of the result register (13) when an overflow occurs but otherwise selects the said input data.
Claim 5
Dependent Claim
39 words
A digital circuit according to claim 1, 2 or 3, characterised in that the shifter (15) shifts a plurality of bits of the data from the multiplexer (16), simultaneously, according to the content of the shift control register (14).
Claim 6
Dependent Claim
128 words
A digital circuit comprising input means (11) for inputting data, means (12) for executing an arithmetic operation, means (13) for storing a result of the arithmetic operation, first means (16) for applying the data to one input of the executing means, second means for applying the result stored in the storing means (13) to the other input of the executing means, means (16, 15, 12) for performing a shift operation on the result when the executing means (12) generates a signal indicating an overflow, means (14) for generating information indicating a number of overflows, and second means (16, 14, 15) for performing a shift oepration on the data from the input means (11) according to the said number before this data is transferred to the executing means (12).
Claim 7
Dependent Claim
128 words
A digital circuit comprising input means (11) for inputting data, means (12) for executing an arithmetic operation, means (13) for storing a result of the arithmetic operation, first means (16) for applying the data to one input of the executing means, second means for applying the result stored in the storing means (13) to the other input of the executing means, means (16, 15, 12) for performing a shift operation on the result when the executing means (12) generates a signal indicating an overflow, means (14) for generating information indicating a number of overflows, and second means (16, 14, 15) for performing a shift oepration on the data from the input means (11) according to the said number before this data is transferred to the executing means (12).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.