Multiprocessor storage serialization apparatus

Claim 2

Storage serialization apparatus for a multiprocessor computer system characterized in that it comprises: registering means for registering the page portion of a storage address during a granted storage access indicating which page in storage is being addressed, comparing means for comparing the page portion of a storage address for a requested storage access with said page portion of a storage address registered by said registering means, and means for generating a storage request reject signal when said comparing means indicates a comparison and for generating a storage request granted signal when said comparing means indicates a noncomparison.

Claim 3

Storage serialization apparatus for a multiprocessor computer system including a plurality of processors (10, 20, 30, 40) coupled to a common main storage (100) storing instructions and operand data, said processors accessing storage with a main storage request signal and a storage address having a page portion and an offset into said page to fetch instructions and operand data for processing by said processors, said storage including a plurality of page frames for storing instructions and operand data and means for generating a main storage granted signal upon completion of a storage access, said storage granted signal being used by said processors as an indication that their main storage request was granted, characterized in that it comprises: a register block for each processor of said plurality of processors, said register block including register means (201, 203, 205, 207) for storing a page address, comparing means for comparing a stored page address with a current page address, settable and resettable indicating means (202, 204, 206, 208)for indicating that a page address has been stored by said register means, first logic means (226, 227, 228, 229) having inputs from an associated processor for receiving a processor main storage request signal, from said comparing means for receiving the results of said comparison and from said indicating means to be conditioned thereby for passing a main storage request reject signal in the absence of a processor main storage request signal when said comparing means provides a signal indicating that the stored page address matches the current page address, and second logic means (221, 222, 223, 224) for controlling the entry of a page address into said register means and the setting of said indicating means; and, gating logic means (216, 217, 218, 219) connected to receive said main storage cycle granted signal from said main storage and connected to receive said main storage request rejected signal from said register blocks whereby in the absence of any main storage request rejected signal said gating logic means passes said main storage cycle granted signal, said second logic means of each register block being responsive to said main storage cycle granted signal passed by said gating logic means and responsive to a processor request signal passes the page address into said register means and sets the indicating means in the absence of an instruction fetch signal from an associated processor, said indicating means being resettable by a reset signal from an associated processor at the end of an instruction cycle whereby said first logic becomes inhibited until said indicating means is again set.

Claim 4

Storage serialization apparatus for a multiprocessor computer system including a plurality of processors (10, 20, 30, 40) coupled to a common main storage (100) storing instructions and operand data, said processors accessing storage with a main storage request signal and a storage address having a page portion and an offset into said page to fetch instructions and operand data for processing by said processors, said storage including a plurality of page frames for storing instructions and operand data and means for generating a main storage granted signal upon completion of a storage access, said storage granted signal being used by said processors as an indication that their main storage request was granted, characterized in that it comprises: a register block for each processor of said plurality of processors, said register block including register means (201, 203, 205, 207) for storing a page address, comparing means for comparing a stored page address with a current page address, settable and resettable indicating means (202, 204, 206, 208)for indicating that a page address has been stored by said register means, first logic means (226, 227, 228, 229) having inputs from an associated processor for receiving a processor main storage request signal, from said comparing means for receiving the results of said comparison and from said indicating means to be conditioned thereby for passing a main storage request reject signal in the absence of a processor main storage request signal when said comparing means provides a signal indicating that the stored page address matches the current page address, and second logic means (221, 222, 223, 224) for controlling the entry of a page address into said register means and the setting of said indicating means; and, gating logic means (216, 217, 218, 219) connected to receive said main storage cycle granted signal from said main storage and connected to receive said main storage request rejected signal from said register blocks whereby in the absence of any main storage request rejected signal said gating logic means passes said main storage cycle granted signal, said second logic means of each register block being responsive to said main storage cycle granted signal passed by said gating logic means and responsive to a processor request signal passes the page address into said register means and sets the indicating means in the absence of an instruction fetch signal from an associated processor, said indicating means being resettable by a reset signal from an associated processor at the end of an instruction cycle whereby said first logic becomes inhibited until said indicating means is again set.

Claim 5

The storage serialization apparatus of claim 2 characterized in that said register means (201, 203, 205, 207) includes a first page address register for storing the page address of a first operand or of the first portion of a first operand, a second page address register for storing the page address of the second portion of a first operand, a third page address register for storing the page address of a second operand or of the first portion of a second operand, and a fourth page address register for storing the page address of the second portion of a second operand.

Claim 6

The storage serialization apparatus of claim 2 characterized in that said indicating means is a latch.

Claim 7

The storage serialization apparatus of claim 3 characterized in that said indicating means comprises a latch for each of said first, second, third and fourth page address registers.

Claim 8

The storage serialization apparatus of claim 3 characterized in that further comprises a register selection bus (215)commonly connected to each processor and to said second logic means of each register block for selecting the page address register of said first, second, third and fourth page address register which is to receive the page address.