EP0044400A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
FET memory cell structure and process
Assignee: International Business Machines Corp
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Filing: 1981-06-05
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Granted: —
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Expires: 2001-06-05
Abstract
Abstract A dense, vertical MOSFET memory cell (12) has a high charge storage capacitance per unit area of substrate surface. The charge storage capacitor structure is formed within a well (25) etched in the silicon semiconductor substrate (11) by a combination of reactive ion etching and a self-limiting wet etch.
Inventors
- 👤 Joseph John Fatula, Jr.
- 👤 Paul Louis Garbarino
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 12:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P50/60; H10P50/64; H10P50/642; H10P50/644
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
183 words
A method for producing a dense vertical MOSFET device (12) comprising providing a monocrystalline silicon substrate (11) having a gate including a gate dielectric layer (15) on said substrate (11), a gate electrode layer (13) on said dielectric layer (15) and source and drain regions (17, 19) in said substrate (11) on opposite sides of said gate (13, 15); characterized by the following subsequently applied process steps: reactive ion etching a substantially U-shaped opening (25) into said substrate (11) in said drain region (19) adjacent to said gate (13, 15); growing a silicon dioxide layer (Fig. 12: 59) on the surface (61) of said U-shaped opening (57); reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening (57); etching said deeper opening (57) with a directional etchant to form a well having an enlarged buried opening; removing by etching said silicon dioxide (59) from said well (57); diffusing (Fig. 15) an impurity into the surface (61) of said well (57) and; forming electrical contacts (71, 73) to the source (45) and to said gate electrode layer (41).
Claim 2
Independent Claim
183 words
A method for producing a dense vertical MOSFET device (12) comprising providing a monocrystalline silicon substrate (11) having a gate including a gate dielectric layer (15) on said substrate (11), a gate electrode layer (13) on said dielectric layer (15) and source and drain regions (17, 19) in said substrate (11) on opposite sides of said gate (13, 15); characterized by the following subsequently applied process steps: reactive ion etching a substantially U-shaped opening (25) into said substrate (11) in said drain region (19) adjacent to said gate (13, 15); growing a silicon dioxide layer (Fig. 12: 59) on the surface (61) of said U-shaped opening (57); reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening (57); etching said deeper opening (57) with a directional etchant to form a well having an enlarged buried opening; removing by etching said silicon dioxide (59) from said well (57); diffusing (Fig. 15) an impurity into the surface (61) of said well (57) and; forming electrical contacts (71, 73) to the source (45) and to said gate electrode layer (41).
Claim 3
Dependent Claim
13 words
The method of claim 1 characterized in, that the directional etchant is pyrocatechol.
Claim 4
Dependent Claim
25 words
The method of claim 1 characterized in, that the reactive ion etching of said U-shaped opening (57) is in a fluorene or chlorine containing atmosphere.
Claim 5
Dependent Claim
21 words
The method of claim 1 characterized in, that said substrate (30) is P type silicon and said impurity is N type.
Claim 6
Dependent Claim
12 words
The method of claim 4 characterized in, that said impurity is phosphorous.
Claim 7
Dependent Claim
12 words
The method of claim 4 characterized in, that said impurity is arsenic.
Claim 8
Dependent Claim
28 words
The method of at least claim 1 characterized in, that said enlarged buried opening (57) has faces (61) lying along the (111) crystal planes of said substrate (30).
Claim 9
Dependent Claim
127 words
A MOSFET device manufactured according to at least claim 1, characterized by a monocrystalline silicon substrate (30) whose planar surface has a (100) crystal orientation; a source (45) and a drain (47) formed in said surface, and an insulated gate (39, 41) on said planar surface between said source (45) and drain (47) for selectively rendering a channel in said substrate (30) beneath said gate (30, 41) conductive, said drain (47) including an extended charge storage region formed in the sides (61) of a well (57) in said substrate (30), said well (57) including a first portion having a U-shaped cross section adjacent to said surface and an enlarged second portion beneath said first portion whose faces lie along the (111) planes of said silicon substrate (30).
Claim 10
Dependent Claim
16 words
The device according to claim 8 characterized in, that said substrate (30) is P type silicon.
Claim 11
Dependent Claim
20 words
The device according to 8 and/or claim 9, characterized in, that said charge storage region contains an N type impurity.
Claim 12
Dependent Claim
15 words
The device according to claim 10 characterized in, that said N type impurity is phosphorous.
Claim 13
Dependent Claim
12 words
The device according to claim 10 characterized in, that impurity is arsenic.
Claim 14
Dependent Claim
23 words
The device according to at least claim 8 characterized in, that said gate (39, 41) includes a silicon dioxide gate dielectric layer (39).
Claim 15
Dependent Claim
21 words
The device according to at least claim 8 characterized in that said gate (39, 41) includes a polysilicon gate electrode (41).
References Cited (Backward Citations)
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